SGEA001A December   2019  – April 2021 SN74LVC1G125-Q1

 

  1.   Trademarks
  2. 1Block Diagram
  3. 2Optimizing Gate Driver Control and MCU Communication
  4. 3Logic and Translation Use Cases
    1. 3.1 Logic Use Cases
      1. 3.1.1 Increase Drive Strength
      2. 3.1.2 Gate Driver Control
      3. 3.1.3 Low-Power CAN Wake
    2. 3.2 Voltage Translation Use Cases
      1. 3.2.1 Non-Isolated SPI Communication
      2. 3.2.2 Non-Isolated UART Communication
  5. 4Recommended Logic and Translation Families for On-Board and Wireless Chargers
    1. 4.1 LVC: Low-Voltage CMOS Logic and Translation
    2. 4.2 HCS: Schmitt-Trigger Integrated High-Speed CMOS Logic
  6. 5Revision History

4.1 LVC: Low-Voltage CMOS Logic and Translation

Key features: SN74LVCxxxx

  • Huge portfolio of logic functions
  • LVC: 4+ channels per package
  • Over-voltage tolerant inputs allow unidirectional down-translation with any function
  • High-drive outputs (up to 32 mA)
  • Up to 250 Mbps operation
  • Ioff supports partial-power-down mode operation
  • Packaging options: SOIC, TSSOP, VQFN, SOP, and SSOP

Key features: SN74LVCxGxxxx

  • Put 1, 2, or 3 channels of any logic function right where you need them
  • Configurable gates available ('57, '58, '97, '98, and '99 functions)
  • Over-voltage tolerant inputs allow unidirectional down-translation with any gate or buffer
  • High-drive outputs (up to 32 mA)
  • Up to 250-Mbps operation
  • Ioff supports partial-power-down mode operation
  • Packaging options: SOT-23, SC70, X2SON, SOT-5X3, SON, and DSBGA

Key features: SN74LVCxTxxxx

  • LVCxT: up and down translation across 1.65 V to 5.5 V
  • 1, 2, 8, or 16 channels per device
  • High-drive outputs (up to 32 mA)
  • Up to 250-Mbps operation
  • Ioff supports partial-power-down mode operation

See online parametric search tool to find the right LVC family logic and voltage level translation devices.