2 Optimizing Gate Driver Control and MCU Communication

OBC systems typically contain several isolated gate driver devices to control FETs responsible for the power regulation. Depending on the isolation topology, these gate drivers can require a current drive of up to 20 mA. This may not be an issue if a dedicated PFC controller is used as they typically can source the required current; however, it is common to see other topologies used that utilize a simple MCU or DSP to control the gate drivers for the PFC side and DC/DC side of the system. In this case, it is more likely that additional drive strength is needed and possibly translation up to 5 V from the lower I/O voltage of the MCU.

Figure 2-1 shows an in depth view of how the SN74LVC1G125-Q1 buffer can be used to control an isolated gate driver that uses a opto-couple topology.

Figure 2-1 Example of Logic Buffer Controlling Isolated Gate Driver

In this example, the OE pin of the buffer is being used to control the forward current through the LED. This is one of many different implementations that can be used with a buffer to control the isolated gate driver. This added flexibility is a benefit to adapt to design architecture changes for the ever evolving EV space.

If the signal to the gate driver also needs to be shifted up, this can be done with a voltage translator in the LVC family like the SN74LVC2T45-Q1. Translators in these families have higher drive and can shift up to the 5 V typically required. These voltage translators can also be used for any UART, SPI, or SCI communication between the primary and secondary MCUs if isolation is not required. If isolation is required, the level shifting functionality is typically integrated in the digital isolators from Texas Instruments so additional devices will not be required.