SGLS274I September   2008  – November 2023 UCC27423-Q1 , UCC27424-Q1 , UCC27425-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Dissipation Ratings
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Stage
      2. 7.3.2 Output Stage
      3. 7.3.3 Enable
      4. 7.3.4 Parallel Outputs
      5. 7.3.5 Operational Waveforms and Circuit Layout
      6. 7.3.6 VDD
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Source and Sink Capabilities During Miller Plateau
        2. 8.2.2.2 Drive Current and Power Requirements
      3. 8.2.3 Application Curves
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
  12. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

5 Pin Configuration and Functions

GUID-F9C0226F-770B-48AD-9DB6-A9D631DF9B6E-low.gif Figure 5-1 UCC27423-Q1: D or DGN Package8-Pin SOIC or MSOP With PowerPADDual Inverting, Top View
GUID-DC56D3FD-C75B-42E8-955D-5DA70211CB9A-low.gif Figure 5-2 UCC27424-Q1: D or DGN Package8-Pin SOIC or MSOP With PowerPADDual Noninverting, Top View
GUID-E04FD59E-DF82-438C-BCFE-78F920F58C6E-low.gif Figure 5-3 UCC27425-Q1: D Package8-Pin SOICOne Inverting, One Noninverting, Top View
Table 5-1 Pin Functions
PIN I/O DESCRIPTION
NO. NAME
1 ENBA I Enable input for the driver A with logic-compatible threshold and hysteresis. The driver output can be enabled and disabled with this pin. It is internally pulled up to VDD with 100-kΩ resistor for active high operation. The output state when the device is disabled is low, regardless of the input state.
2 INA I Input A. Input signal of the A driver which has logic-compatible threshold and hysteresis. If not used, this input must be tied to either VDD or GND. It must not be left floating.
3 GND — Common ground. This ground must be connected very closely to the source of the power MOSFET which the driver is driving.
4 INB I Input B. Input signal of the B driver which has logic-compatible threshold and hysteresis. If not used, this input must be tied to either VDD or GND. It must not be left floating.
5 OUTB O Driver output B. The output stage is capable of providing 4-A drive current to the gate of a power MOSFET.
6 VDD — Supply voltage and the power input connection for this device.
7 OUTA O Driver output A. The output stage is capable of providing 4-A drive current to the gate of a power MOSFET.
8 ENBB I Enable input for the driver B with logic-compatible threshold and hysteresis. The driver output can be enabled and disabled with this pin. It is internally pulled up to VDD with 100-kΩ resistor for active-high operation. The output state when the device is disabled is low, regardless of the input state.