SLAA126B April   2001  – September 2018 MSP430F149 , MSP430F149 , TLC3544 , TLC3544 , TLC3548 , TLC3548

 

  1.   Interfacing the TLC3544 or TLC3548 ADC to the MSP430F149 MCU
    1.     Trademarks
    2. 1 Introduction
    3. 2 TLC3544/48 Evaluation Module
    4. 3 Serial Interface
      1. 3.1 Chip Select (CS)
      2. 3.2 Serial Data Input (SDI)
      3. 3.3 Serial Data Output Pin (SDO)
      4. 3.4 Serial Clock Pin (SCLK)
    5. 4 Control and I/O Pins
      1. 4.1 Conversion Start (CSTART)
      2. 4.2 Frame Sync (FS)
      3. 4.3 End of Conversion/Interrupt (EOC/INT)
      4. 4.4 Device Pinout
    6. 5 ADC Initialization and Operation
      1. 5.1 Initializing the ADC
      2. 5.2 Operating the ADC
      3. 5.3 EOC or INT
    7. 6 MSPF149 Code Example
    8. 7 References

3.1 Chip Select (CS)

Chip select is an active-low input signal. When CS is high, the serial-data output (SDO) pin is in a high-impedance state. The serial-data input (SDI) is ignored, and the serial clock (SCLK) is disabled from the internal data clocking circuits. A falling edge of CS, resets the internal 4-bit counter, enables SDI, and removes SDO from its high-impedance state. CS must be held low for the entire sampling period in order to provide valid data conversions (see the TLC3544 data sheet for details).

The chip select signal is shown on the interface section of the EVM schematic as HOST_CNTLa. When HOST_CNTLa is pulled low, the TLC3544/48 ADC is selected.