SLAA126B April   2001  – September 2018 MSP430F149 , MSP430F149 , TLC3544 , TLC3544 , TLC3548 , TLC3548

 

  1.   Interfacing the TLC3544 or TLC3548 ADC to the MSP430F149 MCU
    1.     Trademarks
    2. 1 Introduction
    3. 2 TLC3544/48 Evaluation Module
    4. 3 Serial Interface
      1. 3.1 Chip Select (CS)
      2. 3.2 Serial Data Input (SDI)
      3. 3.3 Serial Data Output Pin (SDO)
      4. 3.4 Serial Clock Pin (SCLK)
    5. 4 Control and I/O Pins
      1. 4.1 Conversion Start (CSTART)
      2. 4.2 Frame Sync (FS)
      3. 4.3 End of Conversion/Interrupt (EOC/INT)
      4. 4.4 Device Pinout
    6. 5 ADC Initialization and Operation
      1. 5.1 Initializing the ADC
      2. 5.2 Operating the ADC
      3. 5.3 EOC or INT
    7. 6 MSPF149 Code Example
    8. 7 References

4.2 Frame Sync (FS)

The FS input signal is normally used in DSP based systems to indicate the start of a serial data frame. If FS is low at the falling edge of CS, the rising edge of the frame sync pulse initiates the sample-and-convert cycle. FS should be pulled to DVDD when not in use.

The TLC3544/48 evaluation module uses a common frame-sync line for both the ADC and DAC. The Xilinx PLD located at U15, acts as a gatekeeper by determining which device (ADC or DAC) should receive the incoming signal. When the HOST_CNTLa line is low (ADC is selected), the PLD routes the incoming FS to the ADC. When HOST_CNTLa is high, the FS signal is applied to the DAC.