SLAA202B February   2005  – December 2018 MSP430F149 , MSP430F149 , MSP430F2252-Q1 , MSP430F2252-Q1 , MSP430F2272-Q1 , MSP430F2272-Q1 , MSP430F2274 , MSP430F2274 , MSP430FG4619 , MSP430FG4619

 

  1.   Implementing IrDA With MSP430™ MCUs
    1.     Trademarks
    2. 1 Introduction
    3. 2 Hardware Description
      1. 2.1 Hardware Overview
      2. 2.2 Circuit Description
    4. 3 Software Description
      1. 3.1 Implementing IrPHY Layer Using Timer_A
        1. 3.1.1 Transmission
        2. 3.1.2 Reception
      2. 3.2 Implementing IrPHY Layer using USCI_A0
      3. 3.3 Implementing IrLAP
        1. 3.3.1 Discovery Services
        2. 3.3.2 Connect Services
        3. 3.3.3 Data Services
        4. 3.3.4 Disconnect Services
      4. 3.4 Implementing IrLMP
        1. 3.4.1 Discovery Services
        2. 3.4.2 Link Connect and Connect Services
        3. 3.4.3 Data Services
        4. 3.4.4 Disconnect Services
      5. 3.5 IAS Implementation
      6. 3.6 TTP Implementation
      7. 3.7 IrCOMM Implementation
      8. 3.8 Application Layer
    5. 4 PC Demonstration Application
    6. 5 IrDA Protocol Basics
      1. 5.1 Physical (IrPHY) Layer
      2. 5.2 Link Access Protocol (IrLAP) Layer
      3. 5.3 Link Management Protocol (IrLMP) Layer
      4. 5.4 Information Access Services (IAS)
      5. 5.5 Tiny Transfer Protocol (TTP)
      6. 5.6 IrCOMM
    7. 6 IrDA Communication Diagram
    8. 7 Frame Exchange Log
    9. 8 References
  2.   Revision History

2.2 Circuit Description

The circuitry around the GP2W0110YPSF is simple (see Figure 1). Two pins are connected to the 3.0-V supply voltage (VCC and LEDA), one pin is connected to the common ground, and three pins interface to the MSP430 (TxD, RxD, and SD). Two bypass capacitors are placed in parallel between VCC and ground close to the transceiver to compensate for current pulses that occur when the transmit IR LED is operated. The TxD and RxD connections are made to Timer_A pins in case of the MSP430F149 (see Figure 1), and to USCI_A0 pins in case of the MSP430FG4619 (see Figure 2) and the MSP430F2274 (see Figure 3).

For the MSP430F149-based design, the device is sourced by a 32-kHz watch crystal that provides a reference clock to calibrate the internal high-speed DCO using a software FLL. This configuration is needed to meet the requirements of the IrPHY physical layer timing specification.

The MSP430FG4619-based design also uses a 32-kHz watch crystal. However, in this case, the built-in FLL circuit of the device clock module generates the system clock.

No external crystal is needed for the MSP430F2274-based design. In this case, the factory-provided DCO calibration constants are loaded into the DCO during device startup, to provide an accurate and stable system clock.

schematic-using-msp430f149.gifFigure 1. Schematic Using MSP430F149
schematic-using-msp430fg4619.gifFigure 2. Schematic Using MSP430FG4619
schematic-using-msp430f2274.gifFigure 3. Schematic Using MSP430F2274