SLAA202B February   2005  – December 2018 MSP430F149 , MSP430F149 , MSP430F2252-Q1 , MSP430F2252-Q1 , MSP430F2272-Q1 , MSP430F2272-Q1 , MSP430F2274 , MSP430F2274 , MSP430FG4619 , MSP430FG4619

 

  1.   Implementing IrDA With MSP430™ MCUs
    1.     Trademarks
    2. 1 Introduction
    3. 2 Hardware Description
      1. 2.1 Hardware Overview
      2. 2.2 Circuit Description
    4. 3 Software Description
      1. 3.1 Implementing IrPHY Layer Using Timer_A
        1. 3.1.1 Transmission
        2. 3.1.2 Reception
      2. 3.2 Implementing IrPHY Layer using USCI_A0
      3. 3.3 Implementing IrLAP
        1. 3.3.1 Discovery Services
        2. 3.3.2 Connect Services
        3. 3.3.3 Data Services
        4. 3.3.4 Disconnect Services
      4. 3.4 Implementing IrLMP
        1. 3.4.1 Discovery Services
        2. 3.4.2 Link Connect and Connect Services
        3. 3.4.3 Data Services
        4. 3.4.4 Disconnect Services
      5. 3.5 IAS Implementation
      6. 3.6 TTP Implementation
      7. 3.7 IrCOMM Implementation
      8. 3.8 Application Layer
    5. 4 PC Demonstration Application
    6. 5 IrDA Protocol Basics
      1. 5.1 Physical (IrPHY) Layer
      2. 5.2 Link Access Protocol (IrLAP) Layer
      3. 5.3 Link Management Protocol (IrLMP) Layer
      4. 5.4 Information Access Services (IAS)
      5. 5.5 Tiny Transfer Protocol (TTP)
      6. 5.6 IrCOMM
    7. 6 IrDA Communication Diagram
    8. 7 Frame Exchange Log
    9. 8 References
  2.   Revision History

3.1.1 Transmission

For transmission, the initial XBOF flags are sent first followed by the BOF flag. Then the rest of the frame is transmitted. The FCS is calculated and sent after the whole frame has been sent, followed by the EOF flag. The actual sending of the individual bytes is performed by fitting each bit into 3/16th of a pulse, where a 0 is represented by a pulse and a 1 is represented by no pulse (see Figure 4). The transmission process is interrupt driven and is handled by the Timer_A module.

ir-byte.gifFigure 4. IR Byte

The actual encoding is manipulated in its entirety by the Timer_A module.

  1. The bit length and 3/16th of the bit length are calculated given the speed at which the Timer_A clock source is operating, and they are stored as constants for use in the transmission process.
  2. Timer_A is cleared and the clock source is set to SMCLK.
  3. The pin being used for transmitting data is configured for the CCR1 peripheral function, and its direction is set to output.
  4. The current state of TAR is stored in register CCR1 which, given that TAR has been previously cleared, holds a value of 0.
  5. One bit length is added to the value stored in CCR1, and then CCR1 is copied into register CCR0.
  6. The number of counts that equal 3/16th of a pulse width is added to CCR0.
  7. The stop bit and start bit are added to the 8 bits of data to be transmitted.
  8. The transmission counter is loaded with 10, to include the start and stop bits.
  9. The CCR0 interrupt is enabled in the CCTL0 control register.
  10. Output Mode 3 Set/Reset is selected for CCR1 to transmit the start bit.
  11. Timer_A is started in continuous mode.
  12. The CCIE flag is polled to determine when the transmission has ended, because the ISR clears the CCIE flag when all bits of the byte have been transmitted. The CCIE flag is polled by a subroutine inside the transmission routine and as soon as the CCIE flag is cleared, the transmission routine returns.
  13. When TAR reaches CCR1, the output goes high and it returns back low when TAR reaches CCR0. This generates the start bit.

Figure 5 shows the switching between the output modes as well as the resulting output signals.

  1. The Timer_A module first adds 1 bit length to CCR1 and CCR0. This keeps them 3/16th of a bit apart from each other but sets them up in time to transmit the next bit.
  2. If the bit is 0, then it is sent using Output Mode 3 Set/Reset which produces a pulse, given that all bits must be sent inverted.
  3. If the bit is 1, then Output Mode 3 is changed to Output Mode 5 Reset to make sure that the output is held low.
  4. When the bit counter reaches 0, the interrupts for CCR0 are disabled and the ISR returns.
transmission-with-timer_a.gifFigure 5. Transmission With Timer_A