SLAA249B April 2005 – September 2018 MSP430F169 , MSP430F169 , MSP430F5252 , MSP430F5252 , MSP430F5253 , MSP430F5253 , MSP430F5254 , MSP430F5254 , MSP430F5255 , MSP430F5255 , MSP430F5256 , MSP430F5256 , MSP430F5257 , MSP430F5257 , MSP430F5258 , MSP430F5258 , MSP430F5259 , MSP430F5259
This application report describes the implementation of the system management bus (SMBus) using the MSP430™ hardware I2C peripheral. SMBus is used as a communication link for smart batteries, power-related devices, and a wide variety of other system devices. This report includes the support for master and slave protocols in a SMBus communication system.
The source code described in this application report is available from http://www.ti.com/lit/zip/slaa249. For additional help enabling communication with SMBus devices, see the MSP430 SMBUS Library.
MSP430 is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
SMBus is a two-wire serial interface based on the principles of I2C. The two lines are serial clock (SCL) and serial data (SDA), which are tied to VCC using pullup resistors. The devices communicating on this bus can drive the lines low or release them to high impedance. This connection is a wired-AND configuration. Multiple I2C or SMBus devices can be connected on the bus, but pins of the MSP430 MCU should not be pulled above VCC. For example, if the VCC of the MSP430 MCU is at 3 V, then all devices on the bus must be pulled up to only 3 V.
A device performing data transfers on the bus can be considered as a master or a slave. Each master and slave device can either be a transmitter (send data) or a receiver (receive data), and the communication on the bus is always initiated by the master by providing a valid start condition and the SCL signal.
Multiple master and slave devices may be connected on the bus, but only one device may master the bus during a data transfer. Since more than one master may simultaneously attempt to take control of the bus and start a transmission, the I2C/SMBus protocol provides an arbitration mechanism that relies on the wired-AND connection of all devices to the bus. A master device that generates a logic high on the SDA bus loses arbitration to a master that generates a logic low on the data bus. The MSP430 MCU master transmitter that loses arbitration switches to slave receiver mode and sets the arbitration lost flag, ALIFG. [1] Each device on the bus has a unique 7-bit address, which allows a total of 128 devices to be connected on the bus. Some addresses are dedicated SMBus addresses that are reserved and must not be assigned to any SMBus device; for example, the SMBus Alert response address (0001 100b). [2]
The different communication protocols can be found in the System Management Bus specification. [2] The communication always begins with a valid start condition from the master followed by a 7-bit slave address and the read/write bit that defines the master as a receiver /transmitter respectively, except in the quick command protocol. In quick command protocol, the read/write bit is used to turn a device on/off or enable/disable a low-power mode. The read/write bit is followed by an Acknowledge from the slave. This is followed by 8-bit transfers that may be data, command, or Packet Error Check (PEC). An acknowledge is sent by the receiver after each byte is received. To end the transfer, a valid stop condition is initiated by the master.
The SMBus standard introduced the Packet Error Checking (PEC) mechanism to improve communication reliability. The PEC is a CRC-8 error check byte, calculated on all message bytes except the ACK, NACK, START, and STOP bits. The PEC is added to the message by the transmitter. The PEC in this application report is calculated using a cyclic redundancy check (CRC-8) polynomial, C(x) = x8 + x2 + x1+ 1 and is calculated bit by bit in the order of bits received. See the SMBus specification for details on the PEC.
Another optional signal defined in the SMBus standard is the SMBALERT signal. This pin is also pulled up to VCC through a resistor. A slave device can signal the master through SMBALERT to request communication with the master. The master acknowledges such a slave device by sending the SMBus alert response address (0001 1001b) on the bus. The slave device acknowledges this Alert command by returning its 7-bit slave address on the bus and the ALERT signal becomes inactive. The eighth bit can be a 0 or 1. If multiple devices pull the SMBALERT signal low, the lowest address device wins arbitration, and its signal becomes inactive after the corresponding slave address byte is put on the bus.
The SMBus operating frequency range is 10 kHz to 100 kHz. Because a minimum speed needs to be maintained in this communication, a slave can hold SCL low for only a specified amount of time before the master times out and issues a stop condition. A slave can hold the clock low for 25 ms before timeout occurs. After this time, the slave must be able to receive a new start condition within 35 ms. Additional timing information can be found on the SMBus specification site (http://www.smbus.org). [2]