3.2.2 SPI Mode
The operation of the MSP430F261x USCI in SPI mode and the MSP430F16x USART is almost identical. The major differences are:
- The MSP430F16x USART supports two channels of simultaneous SPI communication (USART0 and USART1), and the MSP430F261x USCI supports four channels (USCI_A0, USCI_B0, USCI_A1, and USCI_B1).
- On the MSP430F16x, each of the four SPI communication endpoints has a dedicated interrupt vector. On the MSP430F261x, each USCI module has a two shared interrupt vectors, combining transmit and receive events for each module. On both devices, four interrupt vectors are available in total.
- The MSP430F261x USCI defaults to an LSB-first SPI bit order. The bit order can be configured with the UCMSB bit in the UCAxCTL0/UCBxCTL0 control registers. This is different compared to the UART module, where the bit order is MSB first and cannot be configured.
- The maximum MSP430F261x USCI bit clock frequency in SPI master mode is BRCLK, and on the MSP430F16x USART module, it is BRCLK/2.