SLAA396A June   2008  – September 2018 MSP430F5131 , MSP430F5132 , MSP430F5151 , MSP430F5152 , MSP430F5171 , MSP430F5172 , MSP430F5232 , MSP430F5234 , MSP430F5237 , MSP430F5239 , MSP430F5242 , MSP430F5244 , MSP430F5247 , MSP430F5249 , MSP430F5252 , MSP430F5253 , MSP430F5254 , MSP430F5255 , MSP430F5256 , MSP430F5257 , MSP430F5258 , MSP430F5259 , MSP430F5304 , MSP430F5308 , MSP430F5309 , MSP430F5310 , MSP430F5324 , MSP430F5325 , MSP430F5326 , MSP430F5327 , MSP430F5328 , MSP430F5329 , MSP430F5333 , MSP430F5336 , MSP430F5338 , MSP430F5340 , MSP430F5341 , MSP430F5342 , MSP430F5418 , MSP430F5418A , MSP430F5419 , MSP430F5419A , MSP430F5435 , MSP430F5435A , MSP430F5436 , MSP430F5436A , MSP430F5437 , MSP430F5437A , MSP430F5438 , MSP430F5438A , MSP430F5500 , MSP430F5501 , MSP430F5502 , MSP430F5503 , MSP430F5504 , MSP430F5505 , MSP430F5506 , MSP430F5507 , MSP430F5508 , MSP430F5509 , MSP430F5510 , MSP430F5630 , MSP430F5631 , MSP430F5632 , MSP430F5633 , MSP430F5634 , MSP430F5635 , MSP430F5636 , MSP430F5637 , MSP430F5638

 

  1.   MSP430F5xx Overview and Comparison to MSP430F2xx and MSP430F4xx
    1.     Trademarks
    2. 1 Introduction
    3. 2 Memory Mapping
    4. 3 Core Modules
      1. 3.1 Central Processing Unit (CPUX)
      2. 3.2 Power Management Module (PMM)
      3. 3.3 Unified Clock System (UCS)
      4. 3.4 System Module (SYS)
      5. 3.5 JTAG Enhanced Emulation Module (JTAG/EEM)
    5. 4 Peripheral Modules
      1. 4.1 Timer_A
      2. 4.2 Timer_B
      3. 4.3 RTC_A
      4. 4.4 DMA
      5. 4.5 MPY32
      6. 4.6 Universal Serial Communication Interface (USCI)
      7. 4.7 Digital I/O
      8. 4.8 Cyclic Redundancy Check (CRC-CCITT)
      9. 4.9 ADC12_A
  2.   Revision History

4.7 Digital I/O

The Digital I/O has been expanded to include the pullup and pulldown features of the MSP430F2xx family. Each port now contains resistor enable registers (PxREN) for this feature. In addition, the MSP430F5xx supports two output drive settings – low or high drive strength. The output drive strength is set using the PxDS registers. Using low drive strength, whenever possible, helps to reduce unwanted noise. The default setting is low drive strength.

All ports are grouped as pairs of byte-wide ports. Ports can be accessed in byte-wide or word-wide formats. This capability is not available on most MSP430F2xx and MSP430F4xx families.

Interrupt vector generators for Port 1 and 2 have been added, P1IV and P2IV. The interrupt vector generator behaves the same as those seen on MSP430F2xx and MSP430F4xx families on various modules (Timer_A, Timer_B), only now applied to Port 1 and Port 2. This feature is not available on MSP430F2xx and MSP430F4xx families. Any Port 1 or 2 interrupt event that is enabled generates a PC offset that resides in the P1IV or P2IV. This offset can be added to the PC to create a form the basis for simple interrupt handler. Future MSP430F5xx offerings will include additional interrupts on ports other than Ports 1 and 2.

It is important to note that on all MSP430F5xx devices, the crystal input and outputs of XT1 and XT2 (when available) are shared with general-purpose I/O ports. The default reset condition on these pins in general-purpose input ports. This differs from the MSP430F4xx, which does not share the crystal pins, and the MSP430F2xx, which defaults to crystal operation when shared.