SLAA475A October   2010  – March 2019 MSP430L092

 

  1.   MSP430x09x Analog Pool: Feature Set and Advanced Use
    1.     Trademarks
    2. 1 MSP430x09x Overview
    3. 2 Analog Pool (A-Pool)
      1. 2.1  Input Dividers
      2. 2.2  Internal Reference
      3. 2.3  Starting and Stopping the A-Pool
      4. 2.4  Comparator Function
      5. 2.5  8-Bit DAC Function
      6. 2.6  8-Bit ADC Function
        1. 2.6.1 ADC Conversion Using Ramp
          1. 2.6.1.1 ADC Conversion Without Error Compensation
          2. 2.6.1.2 ADC Conversions With Overdrive Compensation
          3. 2.6.1.3 ADC Conversions With Offset Compensation
          4. 2.6.1.4 ADC Conversions With Overall Compensation
          5. 2.6.1.5 Windowed ADC Conversion
        2. 2.6.2 ADC Conversion Using SAR
        3. 2.6.3 Multiple ADC Conversions
        4. 2.6.4 Comparison Between Different Measurement Methods
        5. 2.6.5 Error Dependencies
      7. 2.7  SVM Function
      8. 2.8  Use of Multiple Features
      9. 2.9  Temperature Measurements With the A-Pool
      10. 2.10 Fractional and Integer Number Use
      11. 2.11 APINTB and APFRACTB Use With ATBU and EOCBU
      12. 2.12 A-Pool Trigger Sources
      13. 2.13 Filtering ADC Conversions With Digital Filters
    4. 3 Summary
    5. 4 References
  2.   Revision History

2.12 A-Pool Trigger Sources

The A-Pool has three trigger sources. The triggers can be used to provide specific analog voltages on a dedicated time and can be also used to stop any A-Pool activity.

For stopping the A-Pool, it is possible to use the Timer_A0 capture/compare register 1 (CCR1). To do so, the stop signal must be generated by the application, and the TBSTP bit must be set to one.

Two timer capture compare registers (Timer_A0 CCR0 and Timer_A1 CCR0) can be used to start the A-Pool. To do so, the TA0EN and TA1EN bits must be set accordingly.

The following code shows how to start and stop the A-Pool with Timer_A0. The starting and stopping ADC ramps can be observed on the AOUT pin. The ADC ramp does not stop at a specific voltage level, because no SBSTP or CBSTP bits are set.

#include "msp430l092.h" void main( void ) { // Stop watchdog timer to prevent time out reset WDTCTL = WDTPW + WDTHOLD; TA0CCR0 = 600; // Set start value to 600 TA0CCR1 = 300; // Set stop value to 300 TA0CCTL0 = OUTMOD_3; // Set CCR0 outmode to Set/Reset TA0CCTL1 = OUTMOD_3; // Set CCR0 outmode to Set/Reset TA0CTL = TASSEL_2+MC_1+TACLR; // Set SMCLK to timer clock source + // Set timer to up mode + // Clear timer count register APCNF = CMPON+DBON+CONVON+APREFON+TA0EN; // Enable comparator on + // Enable DAC buffer + // Enable conversion + // Enable reference + // Enable TimerA0 start APCTL = APPSEL0+APPSEL2+OSEL+ODEN+TBSTP; // Set DAC buffer output to PSEL + // Select output buffer + // Enable output driver + // Enable timer based stop while (1); }