SLAA475A October   2010  – March 2019 MSP430L092

 

  1.   MSP430x09x Analog Pool: Feature Set and Advanced Use
    1.     Trademarks
    2. 1 MSP430x09x Overview
    3. 2 Analog Pool (A-Pool)
      1. 2.1  Input Dividers
      2. 2.2  Internal Reference
      3. 2.3  Starting and Stopping the A-Pool
      4. 2.4  Comparator Function
      5. 2.5  8-Bit DAC Function
      6. 2.6  8-Bit ADC Function
        1. 2.6.1 ADC Conversion Using Ramp
          1. 2.6.1.1 ADC Conversion Without Error Compensation
          2. 2.6.1.2 ADC Conversions With Overdrive Compensation
          3. 2.6.1.3 ADC Conversions With Offset Compensation
          4. 2.6.1.4 ADC Conversions With Overall Compensation
          5. 2.6.1.5 Windowed ADC Conversion
        2. 2.6.2 ADC Conversion Using SAR
        3. 2.6.3 Multiple ADC Conversions
        4. 2.6.4 Comparison Between Different Measurement Methods
        5. 2.6.5 Error Dependencies
      7. 2.7  SVM Function
      8. 2.8  Use of Multiple Features
      9. 2.9  Temperature Measurements With the A-Pool
      10. 2.10 Fractional and Integer Number Use
      11. 2.11 APINTB and APFRACTB Use With ATBU and EOCBU
      12. 2.12 A-Pool Trigger Sources
      13. 2.13 Filtering ADC Conversions With Digital Filters
    4. 3 Summary
    5. 4 References
  2.   Revision History

2.7 SVM Function

The A-Pool can be used to implement a supervision voltage monitor function. The integrated VCC divider provides the VCC divided by 8 or divided by 4 for better observation accuracy. A nearly full battery can be easily observed by the VCC divided by 8. Lower battery voltages should be observed with the VCC divided by 4 to get a higher resolution of the supply voltage.

The customer has the choice between a comparator-based and an ADC-based implementation. Using the ADC, the application can measure the internal VCC voltage and can take actions depending on the measured value. The comparator-based solution compares the desired voltage level with the divided VCC voltage.

To generate an SVM, the divided VCC input must be connected to the comparator. Furthermore, the VCCDIVEN bit must be set to 1 to enable the internal VCC ladder. The measured value shows the current VCC value divided by the selected divider. The following code shows a simple VCC observation using the comparator functionality. An SVMIFG flag is generated when the voltage falls below the selected limit. Unlike the SVM functions known from other MSP430 devices, this SVM implementation triggers only one event at the moment when the VCC crosses the selected limit. If the VCC level is below this limit, no additional SVM flag is generated by the logic.

#include "msp430l092.h" void main( void ) { // Stop watchdog timer to prevent time out reset WDTCTL = WDTPW + WDTHOLD; P1DIR |= BIT0; // Indicates VCC crosses SVM level APOMR |= CTEN; // Enable CTEN mode APINT = 163; // Set voltage level 1300mV / 8 = 163mV APVDIV |= VCCDIVEN; // Enable VCC divider APCNF = CMPON+DBON+CONVON+APREFON; // Enable comparator on + // Enable DAC buffer + // Enable conversion + // Enable reference APCTL = APPSEL2+APPSEL1+APNSEL2+APNSEL0+OSEL; // Set voltage divider to PSEL + // Set DAC output to NSEL + // Select output buffer SFRIFG1 &=~ SVMIFG; // Clear SVM flag APCNF |= CMPON; // Start comparison while(1) { if (SFRIFG1 & SVMIFG) // Check if SVM flag is set { P1OUT ^= BIT0; // Indicates VCC crosses SVM level SFRIFG1 &=~ SVMIFG; // Clear SVM flag } } }