SLAA513B December   2011  – February 2022 MSP430G2112 , MSP430G2112 , MSP430G2152 , MSP430G2152 , MSP430G2212 , MSP430G2212 , MSP430G2252 , MSP430G2252 , MSP430G2312 , MSP430G2312 , MSP430G2352 , MSP430G2352 , MSP430G2412 , MSP430G2412 , MSP430G2452 , MSP430G2452

 

  1.   Trademarks
  2. 1Typical Single Time Base Method
  3. 2Multiple Time Base Method
  4. 3Implementing the Multiple Time Base Method in a Custom Application
    1. 3.1 Timer Clock Source Selection
    2. 3.2 Period and Frequency Calculation
    3. 3.3 Duty Cycle Calculation
  5. 4Example Code
    1. 4.1 Method
      1. 4.1.1 ISR for Multiple Frequencies
      2. 4.1.2 ISR for Multiple Frequencies and Duty Cycles (PWM)
    2. 4.2 Included Code Examples
  6. 5Limitations of the Multiple Time Base Method
    1. 5.1 ISR Overhead
    2. 5.2 Maximum Output Frequency vs Number of Signals
    3. 5.3 Power Consumption
  7. 6References
  8. 7Revision History

5.3 Power Consumption

Implementing multiple frequencies on a single timer module can result in higher current consumption than using multiple timer modules. This is because the multiple time base method requires the use of timer interrupts that periodically wake the CPU for servicing, whereas the single-time base method can run completely in hardware. This means that when using the multiple time base method, the CPU is awake for a larger percentage of the time instead of staying in low-power mode. This is related to the tables in Section 5.2, which show that the percentage of time in active mode (ISR time) increases with each additional timer signal and as timer signal frequencies approach the timer clock source frequency. This in turn increases the average power consumption.