SLAA513B December   2011  – February 2022 MSP430G2112 , MSP430G2112 , MSP430G2152 , MSP430G2152 , MSP430G2212 , MSP430G2212 , MSP430G2252 , MSP430G2252 , MSP430G2312 , MSP430G2312 , MSP430G2352 , MSP430G2352 , MSP430G2412 , MSP430G2412 , MSP430G2452 , MSP430G2452

 

  1.   Trademarks
  2. 1Typical Single Time Base Method
  3. 2Multiple Time Base Method
  4. 3Implementing the Multiple Time Base Method in a Custom Application
    1. 3.1 Timer Clock Source Selection
    2. 3.2 Period and Frequency Calculation
    3. 3.3 Duty Cycle Calculation
  5. 4Example Code
    1. 4.1 Method
      1. 4.1.1 ISR for Multiple Frequencies
      2. 4.1.2 ISR for Multiple Frequencies and Duty Cycles (PWM)
    2. 4.2 Included Code Examples
  6. 5Limitations of the Multiple Time Base Method
    1. 5.1 ISR Overhead
    2. 5.2 Maximum Output Frequency vs Number of Signals
    3. 5.3 Power Consumption
  7. 6References
  8. 7Revision History

4.1 Method

In addition to setting up clocks, pins, and other standard MSP430 initialization, there are two main pieces of code that need to be implemented for the multiple time base method – the timer initialization and the timer ISRs. The timer initialization is essentially the same no matter what frequencies you are trying to implement. The following code shows the timer initialization from the file multi_freq_g2452_example.c:

  TACCTL0 = OUTMOD_4 + CCIE;                // CCR0 toggle, interrupt enabled
  TACCTL1 = OUTMOD_4 + CCIE;                // CCR1 toggle, interrupt enabled
  TACCTL2 = OUTMOD_4 + CCIE;                // CCR2 toggle, interrupt enabled
  TACTL = TASSEL_2 +  MC_2 + TAIE;          // SMCLK, Contmode, int enabled

The only things that change in this initialization process, depending on the particular application, are the number of TxCCTLx registers used (which should be set according to the desired number of output frequencies) and the TxSSELx bits in the TxCTL register (which should be set according to the desired timer clock source).

If multiple duty cycles are desired in addition to multiple frequencies, then one more setting is needed for the TxCCTLx registers: the CCISx bits must be set. This is because the ISR for multiple frequencies and duty cycles (see Section 4.1.2) uses the CCI bit to read back the signal on the pin to determine if the output is currently in the high or low phase. The CCISx bits select which signal or pin is connected to the internal CCI signal for that TxCCTLx register – either the pin or signal connected to CCIxA or CCIxB. For this implementation, the user must select the CCISx setting that corresponds to the GPIO pin where they are outputting the PWM. Information about the timer signal connections for each timer module on the device is provided in the device-specific datasheet. The following code shows the timer initialization from the file multi_freq_pwm_g2452_example.c:

  TACCTL0 = CCIS_0 + OUTMOD_4 + CCIE;       // CCR0 toggle, interrupt enabled, CCI0A input
  TACCTL1 = CCIS_0 + OUTMOD_4 + CCIE;       // CCR1 toggle, interrupt enabled, CCI1A input
  TACCTL2 = CCIS_0 + OUTMOD_4 + CCIE;       // CCR2 toggle, interrupt enabled, CCI2A input
  TACTL = TASSEL_2 +  MC_2 + TAIE;          // SMCLK, Contmode, int enabled