Depending on the time bases that are required in the application, an appropriate timer clock source must be selected. The selection depends on several factors – the frequency required, the number of signals being implemented, and the desired resolution.

The clock source must be of a higher frequency than the desired output frequencies. The more signals being implemented on a single timer, the larger the ratio of clock source frequency to desired output frequency needs to be. For further guidance on the minimum clock source frequency needed to generate multiple frequencies, see the data in Section 5.

When possible, it is best to choose a clock whose frequency is a multiple of the desired time base. For example, to generate a 1-kHz time base from a 32.768-kHz crystal on ACLK, the period would be 32.768 kHz / 1 kHz = 32.768. However, the count can only be a whole number, so the period would actually be 33. This means that the generated time base actually has a frequency of 32.768 kHz / 33 ≈ 0.993 kHz, introducing a small amount of error. If the clock source were a 1-MHz DCO, on the other hand, the period would be 1 MHz / 1 kHz = 1000 counts. This does not introduce any additional error, because the clock source frequency is a multiple of the desired time base. Additional error can be introduced, however, from using less accurate clock sources. In general, the amount of error introduced from rounding is relatively low, and the rounding error decreases as the frequency of the source clock increases. Users should weigh the impact of using a higher frequency clock against the power consumption.

If a PWM with a variable duty cycle is going to be produced (as in a motor control or PWM DAC application), then the resolution of the timer needs to be considered. The resolution is determined by the number of clock ticks that make up one period. For example, to generate a 1-kHz time base with the timer sourced from a 32.768-kHz crystal on ACLK, the period would be 32.768 kHz / 1 kHz = 33 counts. This means that there are 33 different possible settings for the PWM duty cycle, so the duty cycle can vary in steps of 1 / 33 = 3.03% duty cycle. For finer granularity, the timer can instead be sourced from the DCO running at 1 MHz. Now the period to generate a 1-kHz frequency is 1 MHz / 1 kHz = 1000 counts. This means that there are 1000 different possible settings for the PWM duty cycle, so the duty cycle can vary in steps of 1 / 1000 = 0.1% duty cycle. Users should weigh the impact of using a higher frequency clock on their power consumption versus their application's PWM resolution requirements.

Equation 1.