In the single time base method of producing PWMs, the TxCCRx registers do not need to be reloaded and the output is produced automatically without ever having to enter an ISR. This means that after the initial timer configuration there is no software overhead, because everything is handled in hardware. For the multiple time base method, an ISR is entered at the end of each high and low period, adding some software overhead.

While the ISRs in the code examples are kept to the smallest length possible, the required operations which add to the software overhead include:

• Wake-up time if coming from a low-power mode
• ISR entry time
• Decision logic for which TxCCRx triggered the interrupt
• Decision logic for what part of the cycle (high/low) just finished (when implementing PWMs only)
• Reloading the TxCCRx register by adding the appropriate period value

This overhead increases for each signal generated, as this adds to the percentage of time spent in the ISR. Problems occur if the number of cycles spent in the ISR is too great compared to the cycles between ISRs (which is set by your period count value), preventing interrupts from being serviced in a timely manner. Therefore, there is a cutoff point that varies depending on the number of TACCRx registers being used due to the latency added by the ISR code. For a particular number of signals being generated this cutoff point, in terms of number of cycles when the timer clock is being sourced from MCLK, remains essentially constant across MCLK frequencies. This is because the value is an indicator of the ratio between ISR cycles and cycles between interrupts. Figure 5-1 shows the constant relationship of the minimum period count yielding reliable signals versus MCLK. This results in turn in a linear relationship between the maximum output frequency and MCLK, as seen in Figure 5-2.

The data in Figure 5-1 was generated from testing on an MSP430G2452 producing three signals of the same period (“worst-case”).

The data points in Figure 5-1 and Figure 5-2 can also be found in Table 5-1.

This data is provided only as a general guideline for the required timer source frequency to produce the desired output frequencies, and should not be regarded as a data sheet specification. Other factors like the other interrupts in the system, the construction of the ISR code, or different frequency and duty cycle combinations may affect the results in a particular application.

Figure 5-1 Minimum Period Count vs MCLK Frequency

The data in Figure 5-2 was generated from testing on an MSP430G2452 producing three signals of the same period (“worst-case”).

The data points in Figure 5-1 and Figure 5-2 can also be found in Table 5-1.

This data is provided only as a general guideline for the required timer source frequency to produce the desired output frequencies, and should not be regarded as a data sheet specification. Other factors like the other interrupts in the system, the construction of the ISR code, or different frequency and duty cycle combinations may affect the results in a particular application.

Figure 5-2 Maximum Output Frequency vs MCLK Frequency