SLAA558A November 2012 – October 2018 MSP430F5212 , MSP430F5214 , MSP430F5217 , MSP430F5219 , MSP430F5222 , MSP430F5224 , MSP430F5229 , MSP430F5252 , MSP430F5253 , MSP430F5254 , MSP430F5255 , MSP430F5256 , MSP430F5257 , MSP430F5258 , MSP430F5259
The MSP430F522x and MSP430F521x devices support a split supply I/O system that is essential in systems in which the MCU is required to interface with external devices (such as sensors or other processors) that operate at different voltage level compared to the MCU device supply. Additionally, the split supply input voltage range of the F522x and F521x devices starts as low as 1.62 V (see the device data sheet specifications), and this allows for nominal 1.8-V I/O interface without the need for external level translation. This application report describes the various design considerations to keep in mind while designing the F522x and F521x devices in an application.
The application report discusses the new features of F522x and F521x devices, which mainly include the split-supply I/O system and the various digital functions supplied from the split-supply I/O rail.
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For split-supply I/O systems, the split supplies are connected to the VCC (DVCC and AVCC) and DVIO pins. Supply voltage at DVCC and AVCC pins (VCC) is used to provide device power, and the supply voltage at the DVIO pin (VIO) is used to supply the I/O rail of the "DVIO supplied I/O pins". The recommended VCC supply voltage ranges from 1.8 V to 3.6 V (see note A on Figure 1) and, therefore, these devices do not operate at nominal 1.8 V (that is, 1.8 V ± 10%) supply voltage level. The VIO supply voltage ranges from 1.62 V to VCC and is useful in applications that interface with nominal 1.8-V I/O interface (that is, 1.8 V ± 10%).
A group of general-purpose I/Os reside on the DVIO supply domain and are called DVIO supplied I/Os. On the MSP430F522x devices, the following I/Os reside on the DVIO supply domain: Port1 (P1.4 to P1.7), Port2, Port3, Port4, and Port7. The remaining port I/Os reside on the DVCC supply domain.
In the data sheet, these I/O ports are highlighted in the functional block diagrams and are also pointed out in the signal descriptions table for respective I/O pins. Also, the electrical characteristics of I/Os in the DVIO and the DVCC domains are specified separately in MSP430F522x, MSP430F521x Mixed-Signal Microcontrollers.
The DVIO supplied general-purpose I/Os are multiplexed with other digital functions in the device, and these digital functions’ I/O circuits are also powered from DVIO. On the F522x and F521x devices, some of the secondary digital functions that are shared with the DVIO supplied I/Os include timer capture compare functions, serial communication functions (USCI UART, SPI, or I2C), comparator output, SMCLK output, and MCLK output. See the signal descriptions table in MSP430F522x, MSP430F521x Mixed-Signal Microcontrollers for details.
On the F522x and F521x devices, Port 4 supports port mapping and resides on the DVIO supply domain. Any of the secondary digital functions specified in the port mapping table can be mapped to Port4, and their respective I/O circuitry is supplied by DVIO. See the port mapping table in the Peripherals section of the data sheet for details.
NOTE
In split supply I/O systems, if external pullup resistors are connected to any of the DVIO supplied pins (for example, the USCI I2C pins – SDA and SCL), tie the external pullups to the DVIO supply and not to DVCC.
Other DVIO supplied digital pins on the F522x and F521x devices include:
For split-supply I/O systems, it is required that the VIO ≥ VCC during the ramp up phase of VIO and VCC. During VCC and VIO power down, it is required that VIO ≥ VCC during the ramp down phase of VIO and VCC. Figure 2 is an excerpt from the data sheet.