SLAA558A November   2012  – October 2018 MSP430F5212 , MSP430F5214 , MSP430F5217 , MSP430F5219 , MSP430F5222 , MSP430F5224 , MSP430F5229 , MSP430F5252 , MSP430F5253 , MSP430F5254 , MSP430F5255 , MSP430F5256 , MSP430F5257 , MSP430F5258 , MSP430F5259

 

  1.   Designing With MSP430F522x and MSP430F521x Devices
    1.     Trademarks
    2. 1 Split-Supply I/O Systems
    3. 2 DVIO Supplied I/Os
    4. 3 Secondary Digital Functions on DVIO Supplied I/Os
    5. 4 Split-Supply Power-Up or Power-Down Sequence
    6. 5 Reset and NMI Pin Functionality
    7. 6 XT1 and XT2 Oscillators in Bypass Mode
    8. 7 Bootloader (BSL)
      1. 7.1 BSL Entry Sequence for DVIO Supplied BSL Interface
      2. 7.2 BSL Exit Sequence for DVIO Supplied BSL Interface
    9. 8 Debugger Connections
      1. 8.1 JTAG Standard Interface
      2. 8.2 Spy-Bi-Wire Interface
      3. 8.3 Debugging Without DVIO
    10. 9 References
  2.   Revision History

5 Reset and NMI Pin Functionality

On the F522x and F521x devices, there are two reset pins:

  • RSTDVCC/SBWTDIO: resides on the DVCC supply domain
  • RST/NMI: resides on the DVIO supply domain

The device can be held in reset by asserting a low on either of the two reset pins. However, the NMI pin functionality is available only on the RST/NMI pin and is not multiplexed with the RSTDVCC pin.

The RSTDVCC pin has an internal pullup that is always enabled and is not configurable. The RST/NMI pin has configurable internal pullup and pulldown resistors available. By default, the internal pullup resistor on the RST/NMI pin is enabled. The SYSRSTUP and SYSRSTRE bits in the reset pin control register (SFRRPCR) are used to select either the internal pullup or pulldown and to enable them, respectively.

If the RST/NMI pin is unused, select and enable the internal pullup resistor, or connect an external pullup resistor (47 kΩ recommended) to the pin.

NOTE

Because all of the 4-wire JTAG pins (on Port J) reside on the DVCC supply domain, use the RSTDVCC pin which also resides on the DVCC supply domain for the JTAG interface and not the DVIO supplied RST/NMI pin. For more details, see the JTAG pin requirements and functions table in MSP430F522x, MSP430F521x Mixed-Signal Microcontrollers.