SLAA600E June 2013 – January 2024
During I2C communication, it is valid for a slave to hold the clock line low when it needs more time to process a packet. This mechanism is known as clock stretching and, although it is very useful, it can also cause devices to hold the bus indefinitely, thus stalling the bus.
The PHY-DL layer can optionally detect when the lines are being held for too long and in such case, the PHY-DL layer can reset the interface.
This feature is enabled depending on CONFIG_CI_PHYDL_TIMEOUT. USCI and USI implementations use TA1 to implement this feature, while eUSCI includes hardware support for it.