SLAA988A December   2020  – January 2022 TAS2563

 

  1.   Trademarks
  2. 1Layout Guidelines
    1. 1.1  Typical Application Circuit
    2. 1.2  VBAT
    3. 1.3  DREG
    4. 1.4  GREG
    5. 1.5  PVDD and VBST
    6. 1.6  VDD
    7. 1.7  IOVDD
    8. 1.8  Output Pins
    9. 1.9  Sense Pins
    10. 1.10 Digital Portion
    11. 1.11 Ground Planes
  3. 2Schematic
    1. 2.1 Recommended External Components
  4. 3Decoupling Capacitors
  5. 4Revision History

Ground Planes

The ground plane routing is important when designing the PCB layout. These planes must be designed to have a proper thermal dissipation and minimize the parasitic impedance as much as possible. Design tips for the different ground pins are listed here:

  • GND pin 28 must be treated like a signal, and connected to GND separately through a via. Do not pour GND plane over pins 27 and 28 together.
  • All other ground pins must be shorted below the package and connected to the PCB ground plane through multiple vias.
  • The vias are the best way to carry heat from the different sections in the board. Since the GND plane will need to quickly dissipate all the elevated temperatures, it is necessary to add multiple vias close to the ground pins.
  • A maximum 150 pH of parasitic inductance is recommended. Having many vias reduces the additional impedance and provides good conduction in both electrical and thermal perspective.
  • An entire layer immediately below the top layer must be dedicated to GND, as best practice.
GUID-20220104-SS0I-ZRH1-FVP8-DCZF4TV8ZDCR-low.png Figure 1-13 GND Pin 28
GUID-20201210-CA0I-5ZG8-PSLM-PQWRLTFDWH0N-low.png Figure 1-14 TAS2x63 Top Layer
GUID-20201210-CA0I-XSVH-8JVT-RWZKZKNCVVSW-low.png Figure 1-15 TAS2x63 Layer 2
GUID-20201210-CA0I-CB0S-ST1P-RKWRGNZ9M3VN-low.png Figure 1-16 TAS2x63 Layer 3
GUID-20201210-CA0I-QQR1-JKJN-FD0JT0Z69HBS-low.png Figure 1-17 TAS2x63 Bottom Layer