SLAAE76B march   2023  – june 2023 MSPM0G1105 , MSPM0G1106 , MSPM0G1107 , MSPM0G1505 , MSPM0G1506 , MSPM0G1507 , MSPM0G3105 , MSPM0G3106 , MSPM0G3107 , MSPM0G3505 , MSPM0G3506 , MSPM0G3507

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 MSPM0G Hardware Design Check List
  5. 2 Power Supplies in MSPM0G Devices
    1. 2.1 Digital Power Supply
    2. 2.2 Analog Power Supply
    3. 2.3 Built-in Power Supply and Voltage Reference
    4. 2.4 Recommended Decoupling Circuit for Power Supply
  6. 3 Reset and Power Supply Supervisor
    1. 3.1 Digital Power Supply
    2. 3.2 Power Supply Supervisor
  7. 4 Clock System
    1. 4.1 Internal Oscillators
    2. 4.2 External Oscillators
    3. 4.3 External Clock Output (CLK_OUT)
    4. 4.4 Frequency Clock Counter (FCC)
  8. 5 Debugger
    1. 5.1 Debug port pins and Pinout
    2. 5.2 Debug Port Connection With Standard JTAG Connector
  9. 6 Key Analog Peripherals
    1. 6.1 ADC Design Considerations
    2. 6.2 OPA Design Considerations
    3. 6.3 DAC Design Considerations
    4. 6.4 COMP Design Considerations
    5. 6.5 GPAMP Design Considerations
  10. 7 Key Digital Peripherals
    1. 7.1 Timer Resources and Design Considerations
    2. 7.2 UART and LIN Resources and Design Considerations
    3. 7.3 MCAN Design Considerations
    4. 7.4 I2C and SPI Design Considerations
  11. 8 GPIOs
    1. 8.1 GPIO Output Switching Speed and Load Capacitance
    2. 8.2 GPIO Current Sink and Source
    3. 8.3 High-Speed GPIOs (HSIO)
    4. 8.4 High-Drive GPIOs (HDIO)
    5. 8.5 Open-Drain GPIOs Enable 5-V Communication Without a Level Shifter
    6. 8.6 Communicate With a 1.8-V Device Without a Level Shifter
    7. 8.7 Unused Pins Connection
  12. 9 Layout Guides
    1. 9.1 Power Supply Layout
    2. 9.2 Considerations for Ground Layout
    3. 9.3 Traces, Vias, and Other PCB Components
    4. 9.4 How to Select Board Layers and Recommended Stack-up
  13. 10Bootloader
    1. 10.1 Bootloader Introduction
    2. 10.2 Bootloader Hardware Design Considerations
      1. 10.2.1 Physical Communication interfaces
      2. 10.2.2 Hardware Invocation
  14. 11References
  15. 12Revision History

7.4 I2C and SPI Design Considerations

SPI and I2C protocols are widely used in communication between devices or boards, such as data exchange between an MCU and a sensor. The MSPM0G series MCU includes up to 32-MHz high-speed SPI, and support 3-wire, 4-wire, chip select, and command mode. Follow Figure 7-6 to design a system based on your requirements.

Some SPI peripheral devices need PICO (Peripherals Input Controller Output) keep high logic. Add a pullup resistor to the PICO pin if your external device requires it.

GUID-20221011-SS0I-D9MN-BKN1-51KLQJPTP7G5-low.svg Figure 7-6 External Connections for Different SPI Configurations

For I2C bus, the MSPM0G device supports Standard, Fast and Fast plus mode, as shown in the Table 7-6.

External pullup resistors are required when using I2C bus. The value of these resistors depends on the I2C speed - TI recommends 2.2k to support Fast mode+. For systems concerned with power consumption, large resistor values can be used. ODIO (see GPIOs) can be used to implement communication with a 5-V device.

Table 7-6 MSPM0G I2C Characteristics
PARAMETERS TEST CONDITIONS Standard mode Fast mode Fast mode plus UNIT
MIN MAX MIN MAX MIN MAX
fI2C I2C input clock frequency I2C in Power Domain0 40 40 40 MHz
fSCL SCL clock frequency 100K 400K 1M MHz
tHD,STA Hold time (repeated) START 4 0.6 0.26 us
tLOW LOW period of the SCL clock 4.7 1.3 0.5 us
tHIGH High period of the SCL clock 4 0.6 0.26 us
tSU,STA Setup time for a repeated START 4.7 0.6 0.26 us
tHD,DAT Data hold time 0 0 0 us
tSU,DAT Data setup time 250 100 50 us
tSU,STO Setup time for STOP 4 0.6 0.26 us
tBUF Bus free time between a STOP and START condition 4.7 1.3 0.5 us
tVD;DAT Data valid time 3.46 0.9 0.45 us
tVD;ACK Data valid acknowledge time 3.46 0.9 0.45 us
GUID-20210322-CA0I-DDHX-QQKB-TQZR3BJ2BQ34-low.svg Figure 7-7 Typical I2C Bus Connection