Subsystem Design
Digital IIR Filter
1 Description
This subsystem demonstrates how the internal ADC, and math accelerator (MATHACL) modules within the MSPM0G family of devices can be used to implement a simple, streaming IIR filter of an analog signal. In this configuration, noise on an analog signal is filtered using a single pole IIR filter. The defined beta value can be adjusted to control the IIR filter decay over frequency.
Figure 1-1 IIR Filter Functional Block
Diagram2 Required Peripherals
Required Peripherals
This application requires an integrated ADC, MathACL, and DAC12 modules.
Table 2-1 Required Peripherals
| Sub-block Functionality | Peripheral Use | Notes |
|---|---|---|
| Analog Signal Capture | (1×) ADC | Shown as ADC12_0_INST in code |
| IIR Filter | (1×) MathACL | Shown as MATHACL in code |
| Analog Signal Output (Optional) | (1×) DAC12 | Shown as DAC12_0_INST in code |
