SLAAEC5 September   2024

 

  1.   1
  2. Description
  3. Required Peripherals
  4. Compatible Devices
  5. Design Steps
  6. Design Considerations
  7. Software Flow Chart
  8. Application Code
  9. Results
  10. Additional Resources
  11. 10E2E
  12. 11Trademarks

Design Steps

  1. Configure the PWM to use shadow registers and interrupts.
  2. Configure the PWM frequency for the desired DAC resolution.
  3. Determine the number of samples needed to adjust the duty cycle. This subsystem example uses 128 samples stored in an array.
  4. Cycle through the sample array. This example increments the array index during the associated ISR, and loads a new compare value to change the duty cycle of the PWM.
  5. Design a low-pass filter for the PWM output, to create the analog voltage. This example uses a single pole RC filter.