SLAAED3A October   2023  – May 2024 TAA5212 , TAA5242 , TAC5111 , TAC5112 , TAC5142 , TAC5211 , TAC5212 , TAC5242

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Analog Input Configuration
    1. 2.1 Differential AC Coupled Configuration
    2. 2.2 Single Ended AC Coupled Configuration
    3. 2.3 Differential DC Coupled Configuration
    4. 2.4 Single Ended DC Coupled Configuration
    5. 2.5 Analog Input Mux Configuration
  6. 3Power Tune Mode and Analog Mixing Feature
    1. 3.1 Differential AC Coupled Power Tune Mode
    2. 3.2 Analog Mixing
  7. 4Summary
  8. 5References
  9. 6Revision History

3.1 Differential AC Coupled Power Tune Mode

When balancing power and performance are needed, the following example provides the register setting for a differential AC-Coupled input with 1.8 V AVDD in power tune mode. Register PWR_TUNE_CFG0 in B0_P0_R78 (0x4E) provides the configuration to place the device into power compensation mode.

Power Tune Mode Differential AC-Coupled Register SettingFigure 3-1 Power Tune Mode Differential AC-Coupled Register Setting
Power Tune Differential AC-Coupled Input at -1dBrG (0dBrG = 1Vrms)Figure 3-2 Power Tune Differential AC-Coupled Input at -1dBrG (0dBrG = 1Vrms)

A frequency plot of the Dynamic Range with -60dBrG input and SNR with input AC signal shorted to ground are provided here.

Power Tune Mode Differential AC-Coupled Dynamic Range at -60dBrGFigure 3-3 Power Tune Mode Differential AC-Coupled Dynamic Range at -60dBrG
Power Tune Mode Differential AC-Coupled SNRFigure 3-4 Power Tune Mode Differential AC-Coupled SNR