SLAAED8 October   2024 TAC5111 , TAC5112 , TAC5211 , TAC5212 , TAC5412-Q1 , TAD5112 , TAD5212

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Signal Generator 1 (SG1)
    1. 2.1 Signal Generator 1 Introduction
    2. 2.2 Signal Generator 1 Amplitude and Output Channels
    3. 2.3 Signal Generator 1 Frequency
    4. 2.4 Generating Register Coefficients Using PPC3
  6. 3ADSR Envelope Parameters
    1. 3.1 ADSR Introduction
    2. 3.2 Restart and Sustain Timers
    3. 3.3 Attack, Release, and Decay Timers
    4. 3.4 Sustain Level
    5. 3.5 ADSR Envelope Example Script
    6. 3.6 Ultrasonic Activity Detection (UAD) ADSR Mode
  7. 4Signal Generator 2 (SG2)
    1. 4.1 Signal Generator 2 Introduction
    2. 4.2 Signal Generator 2 Amplitude
    3. 4.3 Signal Generator 2 Frequency
    4. 4.4 Signal Generator 2 Modes
      1. 4.4.1 Manual Mode
      2. 4.4.2 Continuous Pulse Mode
      3. 4.4.3 One Shot Mode
  8. 5Summary

4.2 Signal Generator 2 Amplitude

Registers B0_P17_R112 (0x70) to B0_P17_R119 (0x77) configure SG2 amplitude. Refer to Programmable Register Map for SG2 Amplitude and Output Channels.

The methods adopted in Section 2.2 transfer to SG2. Implement these I2C and PPC3 concepts on appropriate SG2 registers.

Table 4-1 Programmable Register Map for SG2 Amplitude and Output Channels

Page

Register

Description

Reset Value

0x11

0x70

Side Chain DAC Mixer, SG2 to OUT1M coefficient byte [15:8]

0x00

0x11

0x71

Side Chain DAC Mixer, SG2 to OUT1M coefficient byte [7:0]

0x00

0x11

0x72

Side Chain DAC Mixer, SG2 to OUT1P coefficient byte [15:8]

0x00

0x11

0x73

Side Chain DAC Mixer, SG2 to OUT1P coefficient byte [7:0]

0x00

0x11

0x74

Side Chain DAC Mixer, SG2 to OUT2M coefficient byte [15:8]

0x00

0x11

0x75

Side Chain DAC Mixer, SG2 to OUT2M coefficient byte [7:0]

0x00

0x11

0x76

Side Chain DAC Mixer, SG2 to OUT2P coefficient byte [15:8]

0x00

0x11

0x77

Side Chain DAC Mixer, SG2 to OUT2P coefficient byte [7:0]

0x00