SLAAED9 November 2023 TAA5412-Q1 , TAC5311-Q1 , TAC5312-Q1 , TAC5411-Q1 , TAC5412-Q1
Most of the latched registers in the device are self-clearing and reset upon reading as previously described. However, the mapping of some registers causes the registers to clear only when another latched register is read. Registers that exhibit this behavior include a description in the register map stating which register needs to be read for the bit to clear. This behavior applies to the INxM short to VBAT_IN faults in the channel latch registers as well as the INxP and INxM overvoltage status bits in INT_LTCH1. Reading all latched registers any time a fault is detected is recommended to verify all bits are cleared. To verify no faults are missed, a recommended read sequence is provided in Section 7.3.