SLAAEG3 August   2024 TAC5111-Q1 , TAC5212-Q1 , TAC5311-Q1 , TAC5312-Q1 , TAC5411-Q1 , TAC5412-Q1 , TAD5212-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Signal Chain Architecture
  6. 3ASI Configuration for ICLA
  7. 4Decision Tree
  8. 5Application Example
    1. 5.1 Application Example Script
  9. 6Summary
  10. 7References

Signal Chain Architecture

For systems with up to 8 analog input channels, 8 digital input channels, or 16 digital microphone inputs routed through the DAC signal chain, four TAx5xxx-Q1 devices can synchronize gain adjustments with the ICLA algorithm. TAx5xxx-Q1 supports a shared I2C control bus and audio serial bus using a time-division multiplexed (TDM), Inter-IC Sound (I2S), or Left-justified (LJ) interface. Figure 2-1 shows a diagram of four TA(C/D)5XXX devices connected for ICLA with digital inputs on a shared audio serial bus.

 Playback Signal Path
                Configuration Figure 2-1 Playback Signal Path Configuration

Figure 2-2 shows a diagram of four TAC5xxx-Q1 devices connected for ICLA with 8 analog channels.

 Record and Playback Signal Path
                Configuration Figure 2-2 Record and Playback Signal Path Configuration

Internal ADC channel output loopback is not supported when configuring more than 2 devices for ICLA synchronization due to slot reservation for ICLA communication. Figure 2-3 shows a diagram for routing multiple devices to record and playback with a manual loopback circuit design.

 Record and Playback Path with
                Loopback Figure 2-3 Record and Playback Path with Loopback