SLAAEH2A December   2023  – June 2024 TAA5212 , TAC5111 , TAC5112 , TAC5211 , TAC5212 , TAD5112 , TAD5212

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2TAX5X1X Audio Serial Interface
  6. 3TAX5X1X Synchronous Sampling Rate Converter
    1. 3.1 ADC Sampling Rate Conversion
    2. 3.2 DAC Sampling Rate Conversion
    3. 3.3 SRC Use Case Examples
      1. 3.3.1 Default Mode (Main Fs - Higher rate)
      2. 3.3.2 Default Mode (Main Fs - Higher rate) with Recording
      3. 3.3.3 Custom Mode (Main Fs - Lower rate)
      4. 3.3.4 Custom Mode (Main Fs - Lower rate) with Recording
  7. 4Summary
  8. 5References
  9. 6Revision History

Default Mode (Main Fs - Higher rate) with Recording

Figure 3-6 shows a block diagram for this use case. PASI is running at 48 KHz and SASI is at 16 KHz. In this use case analog input (MIC) sampled at main Fs and down-sampled with SRC to lower rate for SASI. The PASI TX is mixed of sampled MIC input with SASI RX or PASI RX. On the DAC side, SASI RX data can mix with PASI RX data prior to DAC output (Speaker).

 Default Mode diagram with RecordingFigure 3-6 Default Mode diagram with Recording

The Audio Precision APx555 configurations for PASI and SASI are shown below. In this test case, mixer coefficients are kept to its default (full-sacle) and the input levels are adjusted as not to exceed the maximum allowed level for example -9dBrG instead of 0dBrG.

PASI APx555:

Generator:

Analog Output (MIC)∶ 1KHz Sine, -9 dBrG (0dBrG = 2Vrms)

Analyzer:

Input 1∶ Digital audio for PASI  Tx with Fs = 48 KHz, TDM, 32 bit depth

Input 2∶ Analog input from DAC output (Speaker)

SASI APx555:

Generator:

Digital Output∶ 750Hz Sine, -9 dBFS

Analyzer:

Input 1∶ Digital audio for SASI Tx with Fs = 16 KHz, TDM, 32 bit depth

##### PASI higher rate than SASI ADC and DAC SRC Testing with Recording ######
# Target Mode, TDM, 32-bit
# Primary and Secondary ASI, multiple of 48KHz Sampling
# GPIO2=Secondary FSYNC, GPIO1=Secondary BCLK, GPI1=Secondary DIN, GPO1=Secondary DOUT for 4x4
#
w a0 00 00            # Set page 0
w a0 01 01            # Software Reset
w a0 02 09            # Wake up with AVDD > 2v and all VDDIO level
w a0 0a 10            # GPIO1 as input
w a0 0b 10            # GPIO2 as input
w a0 0d 02            # GPI1 as input
w a0 0c 71            # GPO1 as Secondary DOUT
w a0 11 a2            # Enable PASI DIN and Set GPI2A as Secondary FSYNC and GPIO1 as Secondary BCLK
w a0 12 60            # Set GPI1A as Secondary DIN
w a0 18 00            # Enable both Primary and Secondary ASI as independent
w a0 34 40            # PASI BCLK is the input clock source
w a0 19 00            # 1 data input and 1 data output for PASI and SASI
w a0 1a 30            # PASI TDM, 32 bit format
w a0 1e 00            # Tri-state PASI Ch1 to avoid conflict with mix on TDM slot 0
w a0 1f 01            # Tri-state PASI Ch2 to avoid conflict with mix on TDM slot 1
w a0 22 20            # PASI DOUT Ch5 - ASI Loopback data on TDM slot 0
w a0 23 21            # PASI DOUT Ch6 - ASI Loopback data on TDM slot 1
w a0 28 20            # PASI DIN Ch1 on TDM slot 0
w a0 29 21            # PASI DIN Ch2 on TDM slot 1
w a0 00 03            # Set page 3
w a0 1a 30            # SASI TDM, 32 bit format
w a0 1e 20            # SASI DOUT Ch1 on TDM slot 0
w a0 1f 21            # SASI DOUT Ch2 on TDM slot 1
w a0 28 20            # SASI DIN Ch1 on TDM slot 0
w a0 29 21            # SASI DIN Ch2 on TDM slot 1
w a0 00 01            # Set page 1
w a0 17 00            # Default SR-Converter with auto-detect enable
w a0 18 00            # Default auto m:n ratio
w a0 2c d0            # Enable DAC, Side Chain and Loopback Mixer
w a0 00 11            # Set page 0x11
w a0 0c 00 00 40 00   # Route Main DIN Ch1 to LDAC2 Mixer, full scale 
w a0 14 40 00 00 00   # Route Main DIN Ch2 to RDAC2 Mixer, full scale
w a0 4c 00 00 40 00   # Route Aux DIN Ch1 to LDAC2 Mixer, full scale 
w a0 54 40 00 00 00   # Route Aux DIN Ch2 to RDAC2 Mixer, full scale
w a0 5e 40 00         # ADC Loopback Ch1 to SC_LDAC2 Mixer to mix with LDAC2, full scale 
w a0 64 40 00         # ADC Loopback Ch2 to SC_RDAC2 Mixer to mix with RDAC2, full scale
w a0 00 00            # Set page 0
w a0 50 00            # ADC Ch1 diff input, 5KOhm, 2Vrms ac-coupled, audio band
w a0 55 00            # ADC Ch2 diff input, 5KOhm, 2Vrms ac-coupled, audio band
w a0 64 20            # Configure OUT1P/M as differential from DAC1
w a0 65 20            # Configure OUT1P LINEOUT 0dB audio band
w a0 66 20            # Configure OUT1M LINEOUT 0dB 2Vrms Differential 
w a0 6b 20            # Configure OUT2P/M as differential from DAC2
w a0 6c 20            # Configure OUT2P LINEOUT 0dB audio band
w a0 6d 20            # Configure OUT2M LINEOUT 0dB 2Vrms Differential 
w a0 76 cc            # Enable Input and Output Ch1 and Ch2
w a0 78 e0            # Power up ADC, DAC and MICBIAS

Test Results

The following plots show the results of the ADC output at SASI TX after SRC. As expected the frequency response (FFT) ends at 8 KHz (Fs/2 of SASI rate of 1 6KHz).

Figure 3-7 SASI TX 1 KHz tone from MIC input after SRC:

 SASI ADC OutputFigure 3-7 SASI ADC Output

On Speaker output, the tone captured is the SASI RX tone of 750 Hz after SRC. PASI RX tone is muted. PASI TX is a mixed of MIC input with SASI RX tone of 750Hz.

Figure 3-8 shows PASI TX is a mixed of MIC input and SASI RX after SRC.

Figure 3-9 shows 750 Hz tone from SASI RX after SRC, PASI tone is muted:

 PASI ADC OutputFigure 3-8 PASI ADC Output
 Speaker OutputFigure 3-9 Speaker Output