SLAAEH2A December   2023  – June 2024 TAA5212 , TAC5111 , TAC5112 , TAC5211 , TAC5212 , TAD5112 , TAD5212

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2TAX5X1X Audio Serial Interface
  6. 3TAX5X1X Synchronous Sampling Rate Converter
    1. 3.1 ADC Sampling Rate Conversion
    2. 3.2 DAC Sampling Rate Conversion
    3. 3.3 SRC Use Case Examples
      1. 3.3.1 Default Mode (Main Fs - Higher rate)
      2. 3.3.2 Default Mode (Main Fs - Higher rate) with Recording
      3. 3.3.3 Custom Mode (Main Fs - Lower rate)
      4. 3.3.4 Custom Mode (Main Fs - Lower rate) with Recording
  7. 4Summary
  8. 5References
  9. 6Revision History

3 TAX5X1X Synchronous Sampling Rate Converter

TAC5X1X supports synchronous sampling rate converter in ADC and DAC with ratios between the primary and secondary interface shown in Table 3-1. Ratio which is not listed in the table are not supported. Different sampling rates from the table are supported, but the ratio between the PASI and SASI rates must adhere to the ratio listed in the table as interpolators and decimators are designed according to the ratio.

Table 3-1 SRC Supported Ratio
Secondary ASI Rate (KHz)Primary ASI Rate (KHz)
8121624324896
81 : 13 : 22 : 13 : 1Not Supported6 : 1Not Supported
122 : 31 : 14 : 32 : 1Not Supported4 : 1Not Supported
161 : 23 : 41 : 13 : 22 : 13 : 16 : 1
241 : 31 : 22 : 31 : 14 : 32 : 14 : 1
32Not SupportedNot Supported1 : 23 : 41 : 13 : 23 : 1
481 : 61 : 41 : 31 : 22 : 31 : 12 : 1
96Not SupportedNot Supported1 : 61 : 41 : 31 : 21 : 1

In a system with TAC5x1x device, when different sampling rates are detected in PASI and SASI with rates listed in the table above, SRC is automatically enabled without the need of setting SRC_EN bit in B0_P1_R23_D[7] to "1". Sampling rates which are not in the specified list but having the supported ratio are required to set SRC_EN bit to "1" to enable SRC and to set the ratio accordingly in B0_P1_R24_D[5:0]. SRC can be disabled through register B0_P1_R23_D[7] if needed.

SRC in the TAC5X1X has 2 possible modes:

  • Auto-detect Mode: TAC5x1x detects the highest sampling rate (Fs) of the 2 ASI regardless that it is from the Primary ASI or Secondary ASI and consider the higher rate as the main Fs and the lower rate as auxiliary Fs. This is the default mode and TAC5X1X uses higher resources (MIPS) as decimator or interpolator runs at higher rate. The auto-detect mode can be disabled through register B0_P1_R23_D[6].
  • Custom Mode: User decides which ASI; Primary or Secondary sampling frequency to be the main Fs for SRC. This is where lower rate is set as main Fs. This is used where higher use of resources are a concern, but it has disadvantage of losing information on Rx path.