SLAAEI4 August 2024 TAC5111-Q1 , TAC5212-Q1 , TAC5311-Q1 , TAC5312-Q1 , TAC5411-Q1 , TAC5412-Q1 , TAD5212-Q1
Table 3-1 shows the parameters of the Distortion Limiter algorithm. The parameters reside in the 32-bit-wide coefficient memory (page 25 registers) of the device.
Distortion Limiter Parameter | Function and Description |
---|---|
Threshold Maximum (dB) | The maximum peak output signal level, relative to full scale output voltage |
Threshold Minimum (dB) | The minimum peak output signal the Distortion Limiter attenuates to |
Inflection Point (V) | The battery level where the output peak begins to reduce below the threshold maximum |
Slope (V/V) | The rate of output peak decrease from the threshold maximum |
Attack Rate (dB/step) | The step rate response when the Distortion Limiter triggers a gain decrease |
Release Rate (dB/step) | The step rate response when the Distortion Limiter triggers a gain increase |
Hold Counter (ms) | The amount of time taken, following a change in VBAT, before the Distortion Limiter adjusts the output signal level |