SLAAEI4 August   2024 TAC5111-Q1 , TAC5212-Q1 , TAC5311-Q1 , TAC5312-Q1 , TAC5411-Q1 , TAC5412-Q1 , TAD5212-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Signal Processing Chain
  6. 3Distortion Limiter
    1. 3.1 Distortion Limiter Parameters
      1. 3.1.1 Threshold Maximum
      2. 3.1.2 Threshold Minimum
      3. 3.1.3 Inflection Point
      4. 3.1.4 Slope
      5. 3.1.5 Attack Rate
      6. 3.1.6 Release Rate
      7. 3.1.7 Hold Counter
    2. 3.2 Limiter Response
  7. 4Brown-Out Protection
    1. 4.1 Brown-Out Protection Parameters
      1. 4.1.1 Critical Level
      2. 4.1.2 Gain Level
      3. 4.1.3 Attack Rate
      4. 4.1.4 Release Rate
      5. 4.1.5 Hold Counter
    2. 4.2 Brown-Out Protection Response
  8. 5Thermal Foldback
    1. 5.1 Thermal Foldback Parameters
      1. 5.1.1 Temperature Threshold
      2. 5.1.2 Maximum Attenuation Threshold
      3. 5.1.3 Slope
      4. 5.1.4 Attack Coefficient
      5. 5.1.5 Release Coefficient
      6. 5.1.6 Hold Counter
        1. 5.1.6.1 Thermal Foldback Response
  9. 6Example
  10. 7Summary
  11. 8References

3.1.2 Threshold Minimum

The threshold minimum is the minimum peak output signal the Distortion Limiter attenuates to. The target level is expressed relative to full scale (dBFS) of the DAC output. This threshold is controlled by the coefficient YRAM_LIM_TH_MIN. Equation 2 shows how to compute the parameters from the desired dB value. The maximum peak range is from -50dB to 24dB and can be programmed in steps of 1x10^-6dB, where MP is the minimum peak level of the signal in dB.

Equation 2. Y R A M _ L I M _ T H R _ M I N   =   r o u n d ( 10 ( ( M P + 3 ) / 20 ) × 2 24 )

Table 3-3 lists the registers corresponding to YRAM_LIM_TH_MIN. The default value (0x007259DB) corresponds to -7dB.

Table 3-3 Programmable Coefficient Registers for Threshold Minimum
Coefficient Page Register Reset Value Description
YRAM_LIM_TH_MIN 0x19 0x70 0x00 LDAC_SF1_BYT1[31:24]
YRAM_LIM_TH_MIN 0x19 0x71 0x00 LDAC_SF1_BYT2[23:16]
YRAM_LIM_TH_MIN 0x19 0x72 0x00 LDAC_SF1_BYT3[15:8]
YRAM_LIM_TH_MIN 0x19 0x73 0x00 LDAC_SF1_BYT4[7:0]