SLAAEM2 October 2024 AM2434
The two-port Ethernet device is used for field devices, to simplify the support of line topology. As each device has already two Ethernet ports with Ethernet switch capability, the line topology can be simply realizes without the need of additional Ethernet hubs or switches.
The device with two physical Ethernet ports is also referred to as a 3-port switch. The device has two physical Ethernet ports and one logical port that connects to the host processor. Some protocols like EtherCAT require a 25MHz common clock for the two Ethernet PHYs and the MAC. This is to reduce RX/TX jitter when transferring the Ethernet frame from MAC to PHY and vice versa. When using independent 25MHz clock, the RX/TX jitter can be in the range of 40ns for 100Mbps and 4ns for 1000Mbps PHY speeds.
Depending on the industrial Ethernet protocol, either two 10/100 Mbps Ethernet PHYs or two 10/100/1000Mbps Ethernet PHYs are deployed. The PHYs connect via MII or RGMII interface to the Ethernet MAC. There is also a sideband signal called Serial Management Interface (SMI), consisting of MDIO and MCD lines, to enable register programming of the Ethernet PHY by the MAC. Programming the Ethernet PHY can be useful if the PHY needs to operate in a specific operation mode that is not already configured at the power up of the Ethernet PHY via the boot-strap configuration. For additional details on the boot-strap, see the DP83826 Deterministic, Low-Latency, Low-Power, 10/100 Mbps, Industrial Ethernet PHY Data Sheet.
The MAC implementation depends on the supported protocol. There is no common MAC as for example EtherCAT and PROFINET use different type of Ethernet frame handling. For the differences in Ethernet frame handling, see Section 2.6. The MAC makes the process data or Ethernet frames available via the shared RAM.
The CPUs runs the industrial Ethernet protocol stack, the peripheral drivers, additional functions (for example, web-server or UPC-UA database) and the customer application. Depending on the software architecture, those software tasks can be split across different CPU cores.