The GREG pin acts as the supply pin for the high-side gate drivers in the boost converter and the Class-D output stages. The GREG pin is powered using the voltage on the VBAT pin.

The following recommendations need to be taken into account when routing the GREG pin on to the PCB:

• The GREG pin needs to be decoupled to the PVDD pin using a capacitor of value 0.1µF (recommendation is to use a 0201 package to minimize ESL and ESR).
• The top plate needs to be connected to the GREG pin, and the bottom plate needs to use a star-connection directly to the PVDD pins, and not to the PVDD PCB plane or the top plate of the PVDD decoupling capacitor, to avoid common inductance to the PVDD pins.
• The voltage rating of the decoupling capacitor must be ≥ 6.3V.
• If the connection is made in inner PCB layers, use multiple vias to reduce parasitic inductance in the path.

Figure 3-5 Incorrect Routing of GREG Decoupling Capacitor

Figure 3-6 Correct Routing of GREG Decoupling Capacitor

Figure 3-7 Placement of GREG Decoupling Capacitor on EVM

Figure 3-8 Connection of GREG Decoupling Capacitor to Inner Layer Using Vias