The PVDD pin correspond to the output of the internal boost converter. The PVDD pin also act as the power source for driving the Class-D output stage when the output power level is higher than the Y-Bridge threshold.

The following recommendations need to be taken into account when routing the PVDD pin on to the PCB:

• When the output power level is beyond the Y-Bridge threshold, the Class-D output stage draws high switching currents from the PVDD pin due to the fast edge rates.
• This pin must not be loaded through external circuitry when the device is operating with the boost converter.
• To minimize voltage ripple on the PVDD pin due to these transient currents, the PVDD pin must be bypassed with capacitors of value ≥ 2 x 22µF or ≥ 3 x 10µF.

  For PVDD<13V bypass capacitor can be reduced to 2 x 10µF or 1 x 22µF.

• This capacitance can see a level of derating due to:
  • Tolerance
  • Voltage coefficient near maximum PVDD voltage
• This derated capacitance must be at least 3µF at 13V.
• The PVDD pin also needs to be bypassed with a low-ESL capacitor (ESL must be ≤ 250pH) of 0.1µF, to minimize the loop inductance from PVDD to PGND. Use a 0201 package capacitor to achieve this bypass. The low-ESL capacitor must be placed as close to the device as possible.
• The decoupling capacitors need to be bypassed to the PGND pin. When bypassing through the PCB ground plane, use multiple vias (a minimum of three vias is recommended), to minimize parasitic inductance between the ground connection on the bypass capacitor and the PGND pin of the device.
• When operating in external PVDD mode, the PVDD pin needs to be connected to the power source using wide traces that are capable of carrying high current, and have low parasitic resistances, to minimize I²R losses.

Figure 3-3 Placement of PVDD Decoupling Capacitors

Figure 3-4 Routing From PVDD