The OUT_P and OUT_N pins correspond to the differential output of the Class-D amplifier. The following guidelines need to be taken into account for routing these pins on the PCB:

• These pins switch from 0 - AVDD in Y-bridge mode, and 0 - PVDD when Y-bridge threshold is exceeded.
• This switching happens at fast edge rates, and results in high switching current at these nodes. Therefore these pins need to be routed to the speaker with wide traces capable of carrying high current.
• When the routing switches into inner layers of the PCB, multiple vias need to be used to provide current carrying capacity, and reduced parasitic inductance.
• The parasitic capacitance on these pins need to be kept to a minimum, since these parasitic capacitance results in increased switching losses, impacting efficiency. If the capacitance is high enough, the switching can also potentially trigger over-current interrupts.
• Since these nodes are high-voltage switching nodes, avoid routing any low-voltage nodes across this path, like BCLK, FSYNC, SDIN, SDOUT, and more, to avoid coupling.

Figure 3-13 Routing of OUT_P/N to Speaker Terminals

Figure 3-14 Routing Below OUT_P/N Paths in Inner PCB Layers