SLAAEM7 September   2024 TAS2120 , TAS2320

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Application Schematics
    1. 2.1 Recommended Component Ratings
    2. 2.2 Reference Schematic
  6. 3Design Guidelines
    1. 3.1  VDD Pin
    2. 3.2  PVDD Pin
    3. 3.3  GREG Pin
    4. 3.4  SW Pin
    5. 3.5  VBAT Pin
    6. 3.6  OUT_P and OUT_N Pins
      1. 3.6.1 Optional EMI Filter on Output
    7. 3.7  IOVDD Pin
    8. 3.8  DREG Pin
    9. 3.9  Digital I/O Pins
    10. 3.10 Ground Pins
    11. 3.11 HW Selection Pins
  7. 4EMI Specific Guidelines
  8. 5Summary
  9. 6References

3.9 Digital I/O Pins

The device contains the following digital I/O pins, all referenced with respect to the IOVDD supply voltage:

  • SEL1 for Hardware Mode selections
  • SEL2_SCL, SEL3_SDA for I2C communication to the device and Hardware Mode selections.
  • SEL4_AD to set the I2C device address and Hardware Mode selections.
  • SEL5_CLASSH for Boost PWM control and Hardware Mode selections.
  • SBCLK, FSYNC, SDIN, SDOUT for the TDM/I2S audio serial interface.
  • IRQz for the device interrupt.
  • SDz for hardware shutdown of the device.

These digital pins need to be routed away from the high-voltage switching nodes (SW, OUT_P, OUT_N), to avoid any coupling, which can corrupt the integrity of the digital signals.

Routing of Digital Lines Away From the High-voltage Switching LinesFigure 3-17 Routing of Digital Lines Away From the High-voltage Switching Lines