The SW pin correspond to the switching input to the internal boost converter of the device. The following recommendations need to be taken into account while routing the power source to the SW pin on the PCB:

• This node is expected to carry high transient current. The node needs to be routed with wide traces with high current carrying capability and minimal parasitic resistance and inductance.
• This node can switch at high voltages. Avoiding routing any low-voltage traces is recommended, including BCLK, FSYNC, SDIN SDOUT and more across this node to avoid coupling.
• Place the inductor that connects to the SW pin close to the device. Using inductors with lower ESR helps to achieve higher efficiency.
• The routing from the power source to the SW inductor must have minimal parasitic resistance to minimize efficiency impact from I²R losses.
• Decouple the SW inductor with a capacitor of value ≥ 10µF, placed as close to the inductor as possible. This placement is meant to reduce ripple on the node stemming from transient currents. This capacitor must be placed between the power source and the inductor, and not between the inductor and the SW pin of the device.
• Minimize parasitic capacitance on the SW node path, to reduce switching losses, which impacts efficiency.
• When the device is operating in external PVDD mode, the SW pin must be left unconnected.

Figure 3-9 Placement of Boost Inductor and Decoupling Capacitor Near SW Pin

Figure 3-10 Routing of Power Source to SW Inductor