SLAAEM7 September   2024 TAS2120 , TAS2320

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Application Schematics
    1. 2.1 Recommended Component Ratings
    2. 2.2 Reference Schematic
  6. 3Design Guidelines
    1. 3.1  VDD Pin
    2. 3.2  PVDD Pin
    3. 3.3  GREG Pin
    4. 3.4  SW Pin
    5. 3.5  VBAT Pin
    6. 3.6  OUT_P and OUT_N Pins
      1. 3.6.1 Optional EMI Filter on Output
    7. 3.7  IOVDD Pin
    8. 3.8  DREG Pin
    9. 3.9  Digital I/O Pins
    10. 3.10 Ground Pins
    11. 3.11 HW Selection Pins
  7. 4EMI Specific Guidelines
  8. 5Summary
  9. 6References

3.6.1 Optional EMI Filter on Output

The TAS2120 supports edge-rate control to minimize EMI, however the system designer can include passive EMI filter on the Class-D outputs if desired.

When using an EMI filter on the OUT_P or OUT_N pins, the following must be accounted for:

  • The L - C cutoff frequency of the filter must be > 3MHz to avoid resonance with the Class-D switching frequency.
  • The value of the capacitor, C, used in the filter must be selected, such that the (C / L) ratio is ≤ 1.5. This measure avoids false over-current interrupts during peak output power delivery.