SLAAEM7 September   2024 TAS2120 , TAS2320

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Application Schematics
    1. 2.1 Recommended Component Ratings
    2. 2.2 Reference Schematic
  6. 3Design Guidelines
    1. 3.1  VDD Pin
    2. 3.2  PVDD Pin
    3. 3.3  GREG Pin
    4. 3.4  SW Pin
    5. 3.5  VBAT Pin
    6. 3.6  OUT_P and OUT_N Pins
      1. 3.6.1 Optional EMI Filter on Output
    7. 3.7  IOVDD Pin
    8. 3.8  DREG Pin
    9. 3.9  Digital I/O Pins
    10. 3.10 Ground Pins
    11. 3.11 HW Selection Pins
  7. 4EMI Specific Guidelines
  8. 5Summary
  9. 6References

3.7 IOVDD Pin

The IOVDD pin is the power supply pin for the digital I/Os of the device. The following recommendations need to be taken into account while routing the IOVDD pin on to the PCB:

  • Decouple the IOVDD pin to GND using a capacitor of value ≥ 1µF, placed as close to the device as possible.
Placement of IOVDD Decoupling CapacitorFigure 3-15 Placement of IOVDD Decoupling Capacitor