SLAAEM7 September   2024 TAS2120 , TAS2320

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Application Schematics
    1. 2.1 Recommended Component Ratings
    2. 2.2 Reference Schematic
  6. 3Design Guidelines
    1. 3.1  VDD Pin
    2. 3.2  PVDD Pin
    3. 3.3  GREG Pin
    4. 3.4  SW Pin
    5. 3.5  VBAT Pin
    6. 3.6  OUT_P and OUT_N Pins
      1. 3.6.1 Optional EMI Filter on Output
    7. 3.7  IOVDD Pin
    8. 3.8  DREG Pin
    9. 3.9  Digital I/O Pins
    10. 3.10 Ground Pins
    11. 3.11 HW Selection Pins
  7. 4EMI Specific Guidelines
  8. 5Summary
  9. 6References

2 Application Schematics

The following figures show the various configurations that the TAS2x20 can be connected in. Figure 2-1 shows the TAS2120 in 1S configuration, where a single-cell battery is used as the voltage source to power up the device.

TAS2120 in 1S Configuration Figure 2-1 TAS2120 in 1S Configuration

Figure 2-2 shows the device being connected in 2S configuration, with a 2-cell battery acting as the power source for the device.

TAS2120 in 2S Configuration Figure 2-2 TAS2120 in 2S Configuration

Figure 2-3 shows an external PVDD configuration for the TAS2320 where the internal boost converter of the device is disabled, and the PVDD can be provided externally from a 3-cell battery.

TAS2320 in External PVDD Configuration Figure 2-3 TAS2320 in External PVDD Configuration