SLAAEM9 June   2024 TMUXHS4446

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2USB Type-C Alt Mode Application
    1. 2.1 What is Type-C Alt Mode?
    2. 2.2 Why USB Type-C Alt Mode Need Multiplexer
    3. 2.3 When to Use Passive Multiplexer for Type-C Alt Mode application
  6. 3Type-C Alt Mode Application with Passive Multiplexer TMUXHS4446
    1. 3.1 Type-C Alt Mode Source Application
    2. 3.2 Type-C Alt Mode Sink Application
    3. 3.3 Pin Assignment for Source and Sink Application
  7. 4PCB Design For TMUXHS4446
  8. 5Summary
  9. 6References

4 PCB Design For TMUXHS4446

Before start PCB design for Type-C alt mode with TMUXHS4446, we need to get all insertion loss information of TMUXHS4446 mux, PCB board material used and dielectric constant of the material, Table 4-1 list the insertion loss information with FR4 material.

Table 4-1 Insertion Loss Budget for System
1 in trace of FR4 PCB TMUXHS4446 Max insertion loss allowed
Insertion loss at 5.4Gbps (DP1.2) -0.77dB -1.2dB 8 in FR4 trace
Insertion loss at 8Gbps (DP1.4) -1.07dB -1.4dB
Insertion loss at 10Gbps (USB3.0) -1.32dB -1.6dB Max 8.5dB allowed for SSTX or SSRX

For USB3.2 10Gbps, max allowed insertion loss for TX or RX is 8.5dB loss from USB3.2 host to type-C connector. So max trace length is about 5".

For DP 1.2 at 5.4Gbps , Intel recommends maximum 8” DP 1.2 trace without passive MUX . Recommended 1.2dB loss of mux is equal to 1.5 in of PCB trace. So max trace length of DP1.2 is about 6.5".

For DP1.4 at 8Gbps, recommend max trace length is about 4" based on Table 4-1

For PCB layout , the guideline is as follows:

  • Minimize the trace length to prevent channel loss
  • Don’t use EMI chokes, TMUXHS4446 is passive switch which has not having EMI issues
  • Recommend 90 ohm differential impedance trace for differential DP and USB 3.0 signals
  • The trace length miss-matching shall be less than 5 mils for the “+” and “–“
  • Minimize the number of VIAS to prevent loss., No more than two VIAS on single trace from host to Type-C connector, adding ground VIAS next to the VIAS on the trace
  • Route all high-speed differential pairs together symmetrically and parallel to each other
  • Do not place probe or test points on any high-speed differential signal

For a comprehensive guide covering high-speed layout recommendations, see the High-Speed Interface Layout Guidelines application note.