SLAAEO3 September   2024 MSPM0L2227 , MSPM0L2228

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction: MSPM0 and LCD End Applications
  5. 2MSPM0 LCD Portfolio
  6. 3Segmented LCD Operation
    1. 3.1 LCD Structure (Simplified)
    2. 3.2 LCD Drive Basics
  7. 4MSPM0 LCD Features
    1. 4.1 Muxing
      1. 4.1.1 Muxing Example
    2. 4.2 Voltage Generation
      1. 4.2.1 Charge Pump
      2. 4.2.2 Contrast Control
    3. 4.3 LCD Clocking
    4. 4.4 LCD Memory and Blinking Mode
      1. 4.4.1 LCD Memory Organization
      2. 4.4.2 Blinking
    5. 4.5 LCD Output Pin Configuration
    6. 4.6 Low Power Mode Feature
  8. 5LCD Layout and Software Considerations
    1. 5.1 LCD Layout Tips
      1. 5.1.1 Hardware-Driven Layout
      2. 5.1.2 Software-Driven Layout
      3. 5.1.3 General Layout Rules
    2. 5.2 LCD Software Tips
      1. 5.2.1 Create a Look-up Table
      2. 5.2.2 Use of #defines
      3. 5.2.3 Efficient Clearing of the LCD Memory
      4. 5.2.4 Double-buffering of the Display Buffer Using Dual Display Memory
  9. 6Additional Resources

4.3 LCD Clocking

MSPM0 LCD modules include a internal timing generation that does not require timer modules. Figure 4-5 is the LCD clock module diagram in MSPM0 device.

MSPM0L222x LCD Clock Module Diagram Figure 4-5 LCD Clock Module Diagram

The LCD module is sourced by the LFCLK. To achieve the desired frequency for fCLKLCD, scale and divide within the module. fCLKLCD frequencies are usually low (<1kHz), so typically the timing for the module is sourced from low-frequency LFCLK, this clock is also typically available in low-power modes (except SHUTDOWN mode). fCLKLCD is the frequency that generates the timing for the common COMx and segment Sx signals. As shown in the below Table 4-4, when the MUX mode (LCDMXx) is set, the MUXDIVIDER is set automatically corresponding to the LCDMXx. Users are able to change the LCDCTL0.LCDDIVx to control the output frequency of the fCLKLCD.

Table 4-4 CLKLCD Calculation
Clock Equation
CLKLCD fCLKLCD = fCLKLFCLK ÷ ( LCDCTL0.LCDDIVx + 1 ) × MUXDIVIDER
LCDMXx MUXDIVIDER
0 64
1 32
2 16
3 16
4 12
5 8
6 8
7 8

fCLKFRAME is the frame frequency from LCD display's datasheet. The display has a range of allowed frame frequencies, which gives the user options when choosing an fCLKLCD. Lower frequencies lead to lower current consumption, while higher frequencies result in less flickering on the display. Experiment with different fCLKLCD frequencies to determine what setting yields an acceptable appearance on the LCD with the least current consumption. Calculate the required fCLKFRAME using Equation 2.

Equation 2. f C L K F R A M E = f C L K L C D ÷ L C D C T L 0 . L C D M X x + 1 × 2

For example, Equation 3 and Equation 4 show the outcome with a 4-mux mode, where LCDCTL0.LCDMXx is 3, and LCDCTL0.LCDDIVx is 0.

Equation 3. fCLKLCD= 32768÷0+1×16=2048h=Hz
Equation 4. fCLKFRAME= 2048÷3+1×2=256Hz

fCLKBLK is used to flash the segments on and off when blinking is enabled. Segments are turned off when CLKBLK is 0. The required fCLKBLK is calculated using Equation 5.

Equation 5. fCLKBLK= fCLKFRAME÷2LCDBLKPREx+1

fCLKCP is used to generate four phase clocks to the charge pump module, when the charge pump is enabled. The charge pump operates by transferring charge from load capacitor connected between LOADCAP0 and LOADCAP1 pins to other capacitors connected between R33, R23, R24, R13 and ground. The charge pump requires four non-overlapping clocks to control the switches. The required fCLKCP is calculated using Equation 6.

Equation 6. f C L K C P =   f C L K L K C L K ÷ L C D V C T L . L C D C P F S E L x + 1

fCLKVBST is used to boost the voltage on control signals used to control the switches, its frequency is same as LFCLK.