SLAS553B November 2008 – August 2015 TLV320ADC3101
PRODUCTION DATA.
MIN | MAX | UNIT | ||
---|---|---|---|---|
AVDD to AVSS | –0.3 | 3.9 | V | |
IOVDD to DVSS | –0.3 | 3.9 | V | |
DVDD to DVSS | –0.3 | 2.5 | V | |
Digital input voltage to DVSS | –0.3 | IOVDD + 0.3 | V | |
Analog input voltage to AVSS | –0.3 | AVDD + 0.3 | V | |
Operating temperature | –40 | 85 | °C | |
TJ Max | Junction temperature | 105 | °C | |
Power dissipation | (TJ Max – TA) / θJA | W | ||
Tstg | Storage temperature | –65 | 125 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±1000 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±250 |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
AVDD(1) | Analog supply voltage | 2.6 | 3.3 | 3.6 | V |
DVDD(1) | Digital core supply voltage | 1.65 | 1.8 | 1.95 | V |
IOVDD(1) | Digital I/O supply voltage | 1.1 | 1.8 | 3.6 | V |
VI | Analog full-scale 0-dB input voltage (AVDD = 3.3 V) | 0.707 | Vrms | ||
Digital output load capacitance | 10 | pF | |||
TA | Operating free-air temperature | –40 | 85 | °C |
THERMAL METRIC(1) | TLV320ADC3101 | UNIT | |
---|---|---|---|
RGE (VQFN) | |||
24 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 33.9 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 34.1 | °C/W |
RθJB | Junction-to-board thermal resistance | 11.5 | °C/W |
ψJT | Junction-to-top characterization parameter | 0.4 | °C/W |
ψJB | Junction-to-board characterization parameter | 11.5 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | 3.2 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
AUDIO ADC | |||||||
Input signal level (0-dB) | Single-ended input | 0.707 | Vrms | ||||
Input common-mode voltage | Single-ended input | 1.35 | Vrms | ||||
SNR | Signal-to-noise ratio, A-weighted(1)(2) |
fS = 48 kHz, 0-dB PGA gain, IN1 inputs selected and AC-shorted to ground |
80 | 92 | dB | ||
Dynamic range, A-weighted(1)(2) |
fS = 48 kHz, 1-kHz –60-dB full-scale input applied at IN1 inputs, 0-dB PGA gain | 92 | dB | ||||
THD | Total harmonic distortion | fS = 48 kHz, 1-kHz –2-dB full-scale input applied at IN1 inputs, 0-dB PGA gain | –90 | –75 | dB | ||
0.003% | 0.017% | ||||||
PSRR | Power supply rejection ratio | 234 Hz, 100 mVPP on AVDD, single-ended input | 46 | dB | |||
234 Hz, 100 mVPP on AVDD, differential input | 68 | ||||||
ADC channel separation | 1 kHz, –2 dB IN1L to IN1R | –73 | dB | ||||
ADC gain error | 1 kHz input, 0-dB PGA gain | 0.7 | dB | ||||
ADC programmable-gain amplifier maximum gain | 1-kHz input tone, RSOURCE < 50 Ω | 40 | dB | ||||
ADC programmable-gain amplifier step size | 0.502 | dB | |||||
Input resistance | IN1 inputs, routed to single ADC Input mix attenuation = 0 dB |
35 | kΩ | ||||
IN2 inputs, input mix attenuation = 0 dB | 35 | ||||||
IN1 inputs, input mix attenuation = –6 dB | 62.5 | ||||||
IN2 inputs, input mix attenuation = –6 dB | 62.5 | ||||||
Input capacitance | 10 | pF | |||||
Input level control minimum attenuation setting | 0 | dB | |||||
Input level control maximum attenuation setting | 6 | dB | |||||
Input level control attenuation step size | 6 | dB | |||||
ADC DIGITAL DECIMATION FILTER | fS = 48 kHz | ||||||
Filter gain from 0 to 0.39 fS | Filter A, AOSR = 128 or 64 | ±0.1 | dB | ||||
Filter gain from 0.55 fS to 64 fS | Filter A, AOSR = 128 or 64 | –73 | dB | ||||
Filter group delay | Filter A, AOSR = 128 or 64 | 17/fS | s | ||||
Filter gain from 0 to 0.39 fS | Filter B, AOSR = 64 | ±0.1 | dB | ||||
Filter gain from 0.60 fS to 32 fS | Filter B, AOSR = 64 | –46 | dB | ||||
Filter group delay | Filter B, AOSR = 64 | 11/fS | s | ||||
Filter gain from 0 to 0.39 fS | Filter C, AOSR = 32 | ±0.033 | dB | ||||
Filter gain from 0.28 fS to 16 fS | Filter C, AOSR = 32 | –60 | dB | ||||
Filter group delay | Filter C, AOSR = 32 | 11/fS | s | ||||
MICROPHONE BIAS | |||||||
Bias voltage | Programmable settings, load = 750 Ω | 2 | V | ||||
2.25 | 2.5 | 2.75 | |||||
AVDD – 0.2 | |||||||
Current sourcing | 2.5-V setting | 4 | mA | ||||
Integrated noise | BW = 20 Hz to 20 kHz, A-weighted, 1-μF capacitor between MICBIAS and AGND | 3.3 | μV rms |
||||
DIGITAL I/O | |||||||
VIL | Input low level | IIL = 5 μA | –0.3 | 0.3 × IOVDD | V | ||
VIH | Input high level(3) | IIH = 5 μA | 0.7 × IOVDD | V | |||
VOL | Output low level | IIH = 2 TTL loads | 0.1 × IOVDD | V | |||
VOH | Output high level | IOH = 2 TTL loads | 0.8 × IOVDD | V | |||
SUPPLY CURRENT | fS = 48 kHz, AVDD = 3.3 V, DVDD = IOVDD = 1.8 V | ||||||
Mono record | AVDD | PLL and AGC off | 2 | mA | |||
DVDD | 1.9 | ||||||
Stereo record | AVDD | PLL and AGC off | 4 | mA | |||
DVDD | 2.1 | ||||||
PLL | AVDD | Additional power consumed when PLL is powered | 1.1 | mA | |||
DVDD | 0.8 | ||||||
Power down | AVDD | All supply voltages applied, all blocks programmed in lowest power state | 0.04 | μA | |||
DVDD | 0.7 |
PACKAGE TYPE | TA = 25°C POWER RATING |
DERATING FACTOR | TA = 75°C POWER RATING |
TA = 85°C POWER RATING |
---|---|---|---|---|
VQFN | 1.7 W | 22 mW/°C | 665 mW | 444 mW |
IOVDD = 1.8 V | IOVDD = 3.3 V | UNIT | ||||
---|---|---|---|---|---|---|
MIN | MAX | MIN | MAX | |||
td(WS) | BCLK/WCLK delay time | 20 | 15 | ns | ||
td(DO-WS) | BCLK/WCLK to DOUT delay time | 25 | 20 | ns | ||
td(DO-BCLK) | BCLK to DOUT delay time | 20 | 15 | ns | ||
tr | Rise time | 20 | 15 | ns | ||
tf | Fall time | 20 | 15 | ns |
IOVDD = 1.8 V | IOVDD = 3.3 V | UNIT | ||||
---|---|---|---|---|---|---|
MIN | MAX | MIN | MAX | |||
td(WS) | BCLK/WCLK delay time | 25 | 15 | ns | ||
td(DO-BCLK) | BCLK to DOUT delay time | 25 | 15 | ns | ||
tr | Rise time | 20 | 15 | ns | ||
tf | Fall time | 20 | 15 | ns |
IOVDD = 1.8 V | IOVDD = 3.3 V | UNIT | ||||
---|---|---|---|---|---|---|
MIN | MAX | MIN | MAX | |||
tH(BCLK) | BCLK high period | 35 | 35 | ns | ||
tL(BCLK) | BCLK low period | 35 | 35 | ns | ||
ts(WS) | BCLK/WCLK set-up time | 10 | 6 | ns | ||
th(WS) | BCLK/WCLK hold time | 10 | 6 | ns | ||
td(DO-WS) | BCLK/WCLK to DOUT delay time (for LJF Mode only) | 30 | 30 | ns | ||
td(DO-BCLK) | BCLK to DOUT delay time | 25 | 20 | ns | ||
tr | Rise time | 16 | 8 | ns | ||
tf | Fall time | 16 | 8 | ns |
IOVDD = 1.8 V | IOVDD = 3.3 V | UNIT | ||||
---|---|---|---|---|---|---|
MIN | MAX | MIN | MAX | |||
tH(BCLK) | BCLK high period | 35 | 35 | ns | ||
tL(BCLK) | BCLK low period | 35 | 35 | ns | ||
ts(WS) | BCLK/WCLK set-up time | 10 | 8 | ns | ||
th(WS) | BCLK/WCLK hold time | 10 | 8 | ns | ||
td(DO-BCLK) | BCLK to DOUT delay time | 25 | 20 | ns | ||
tr | Rise time | 15 | 8 | ns | ||
tf | Fall time | 15 | 8 | ns |