SLAS564H
August 2007 – July 2024
CDCE937
,
CDCEL937
PRODUCTION DATA
1
1
Features
2
Applications
3
Description
4
Pin Configuration and Functions
5
Specifications
5.1
Absolute Maximum Ratings
5.2
ESD Ratings
5.3
Recommended Operating Conditions
5.4
Thermal Information
5.5
Electrical Characteristics
5.6
Timing Requirements: CLK_IN
5.7
Timing Requirements: SDA/SCL
5.8
EEPROM Specification
5.9
Typical Characteristics
6
Parameter Measurement Information
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
Control Terminal Setting
7.3.2
Default Device Setting
7.3.3
SDA/SCL Serial Interface
7.3.4
Data Protocol
7.4
Device Functional Modes
7.4.1
SDA/SCL Hardware Interface
7.5
Programming
8
Register Maps
8.1
SDA/SCL Configuration Registers
9
Application and Implementation
9.1
Application Information
9.2
Typical Application
9.2.1
Design Requirements
9.2.2
Detailed Design Procedure
9.2.2.1
Spread Spectrum Clock (SSC)
9.2.2.2
PLL Frequency Planning
9.2.2.3
Crystal Oscillator Start-Up
9.2.2.4
Frequency Adjustment With Crystal Oscillator Pulling
9.2.2.5
Unused Inputs and Outputs
9.2.2.6
Switching Between XO and VCXO Mode
9.2.3
Application Curves
10
Power Supply Recommendations
11
Layout
11.1
Layout Guidelines
11.2
Layout Example
12
Device and Documentation Support
12.1
Device Support
12.1.1
Third-Party Products Disclaimer
12.1.2
Development Support
12.2
Documentation Support
12.2.1
Related Documentation
12.3
Receiving Notification of Documentation Updates
12.4
Support Resources
12.5
Trademarks
12.6
Electrostatic Discharge Caution
12.7
Glossary
13
Revision History
14
Mechanical, Packaging, and Orderable Information
1
Features
Member of Programmable Clock Generator Family
CDCEx913: 1PLL, 3 Outputs
CDCEx925: 2PLL, 5 Outputs
CDCEx937: 3PLL, 7 Outputs
CDCEx949: 4LL, 9 Outputs
In-System Programmability and EEPROM
Serial Programmable Volatile Register
Nonvolatile EEPROM to Store Customer Setting
Flexible Input Clocking Concept
External Crystal: 8MHz to 32MHz
On-Chip VCXO: Pull Range ±150ppm
Single-Ended LVCMOS up to 160MHz
Free Selectable Output Frequency up to 230MHz
Low-Noise PLL Core
PLL Loop Filter Components Integrated
Low Period Jitter (Typical 60ps)
Separate Output Supply Pins
CDCE937: 3.3V and 2.5V
CDCEL937: 1.8V
Flexible Clock Driver
Three User-Definable Control Inputs [S0/S1/S2], for Example, SSC Selection, Frequency Switching, Output Enable or Power Down
Generates Highly Accurate Clocks for Video, Audio, USB, IEEE1394, RFID,
Bluetooth™
, WLAN,
Ethernet™
, and GPS
Generates Common Clock Frequencies Used With
TI DaVinci™
,
OMAP™
, DSPs
Programmable SSC Modulation
Enables 0PPM Clock Generation
1.8V Device Power Supply
Wide Temperature Range –40°C to 85°C
Packaged in TSSOP
Development and Programming Kit for Easy PLL Design and Programming (TI
Pro-Clock™
)