SLAS564H August   2007  – July 2024 CDCE937 , CDCEL937

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements: CLK_IN
    7. 5.7 Timing Requirements: SDA/SCL
    8. 5.8 EEPROM Specification
    9. 5.9 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Control Terminal Setting
      2. 7.3.2 Default Device Setting
      3. 7.3.3 SDA/SCL Serial Interface
      4. 7.3.4 Data Protocol
    4. 7.4 Device Functional Modes
      1. 7.4.1 SDA/SCL Hardware Interface
    5. 7.5 Programming
  9. 8 Register Maps
    1. 8.1 SDA/SCL Configuration Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Spread Spectrum Clock (SSC)
        2. 9.2.2.2 PLL Frequency Planning
        3. 9.2.2.3 Crystal Oscillator Start-Up
        4. 9.2.2.4 Frequency Adjustment With Crystal Oscillator Pulling
        5. 9.2.2.5 Unused Inputs and Outputs
        6. 9.2.2.6 Switching Between XO and VCXO Mode
      3. 9.2.3 Application Curves
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
      2. 12.1.2 Development Support
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  14. 13Revision History
  15. 14Mechanical, Packaging, and Orderable Information

8.1 SDA/SCL Configuration Registers

The clock input, control pins, PLLs, and output stages are user configurable. The following tables and explanations describe the programmable functions of the CDCEx937. All settings can be manually written into the device through the SDA/SCL bus or easily programmed by using the TI Pro-Clock™ software. TI Pro-Clock™ software allows the user to quickly make all settings and automatically calculates the values for optimized performance at lowest jitter.

Table 8-1 SDA and SCL Registers
ADDRESS OFFSET REGISTER DESCRIPTION TABLE
00h Generic Configuration Register Table 8-3
10h PLL1 Configuration Register Table 8-4
20h PLL2 Configuration Register Table 8-5
30h PLL3 Configuration Register Table 8-6

The gray-highlighted bits, described in the Configuration Registers tables in the following pages, belong to the Control Terminal Register. The user can predefine up to eight different control settings. These settings then can be selected by the external control pins, S0, S1, and S2 (see Control Terminal Setting).

Table 8-2 Configuration Register, External Control Terminals
Y1 PLL1 SETTINGS PLL2 SETTINGS PLL3 SETTINGS
EXTERNAL
CONTROL PINS		 OUTPUT
SELECTION		 FREQ.
SELECTION		 SSC
SELECTION		 OUTPUT
SELECTION		 FREQ.
SELECTION		 SSC
SELECTION		 OUTPUT
SELECTION		 FREQ.
SELECTION		 SSC
SELECTION		 OUTPUT
SELECTION
S2 S1 S0 Y1 FS1 SSC1 Y2Y3 FS2 SSC2 Y4Y5 FS3 SSC3 Y6Y7
0 0 0 0 Y1_0 FS1_0 SSC1_0 Y2Y3_0 FS2_0 SSC2_0 Y4Y5_0 FS3_0 SSC3_0 Y6Y7_0
1 0 0 1 Y1_1 FS1_1 SSC1_1 Y2Y3_1 FS2_1 SSC2_1 Y4Y5_1 FS3_1 SSC3_1 Y6Y7_1
2 0 1 0 Y1_2 FS1_2 SSC1_2 Y2Y3_2 FS2_2 SSC2_2 Y4Y5_2 FS3_2 SSC3_2 Y6Y7_2
3 0 1 1 Y1_3 FS1_3 SSC1_3 Y2Y3_3 FS2_3 SSC2_3 Y4Y5_3 FS3_3 SSC3_3 Y6Y7_3
4 1 0 0 Y1_4 FS1_4 SSC1_4 Y2Y3_4 FS2_4 SSC2_4 Y4Y5_4 FS3_4 SSC3_4 Y6Y7_4
5 1 0 1 Y1_5 FS1_5 SSC1_5 Y2Y3_5 FS2_5 SSC2_5 Y4Y5_5 FS3_5 SSC3_5 Y6Y7_5
6 1 1 0 Y1_6 FS1_6 SSC1_6 Y2Y3_6 FS2_6 SSC2_6 Y4Y5_6 FS3_6 SSC3_6 Y6Y7_6
7 1 1 1 Y1_7 FS1_7 SSC1_7 Y2Y3_7 FS2_7 SSC2_7 Y4Y5_7 FS3_7 SSC3_7 Y6Y7_7
Address Offset(1) 04h 13h 10h–12h 15h 23h 20h–22h 25h 33h 30h–32h 35h
(1) Address Offset refers to the byte address in the Configuration Register in the following pages.
Table 8-3 Generic Configuration Register
OFFSET(1)BIT(2)ACRONYMDEFAULT(3)DESCRIPTION
00h7E_ELXbDevice identification (read-only): 1 is CDCE937 (3.3 V), 0 is CDCEL937 (1.8 V)
6:4RIDXbRevision Identification Number (read only)
3:0VID1hVendor Identification Number (read only)
01h7–0bReserved – always write 0
6EEPIP0bEEPROM Programming Status:(4) (read only)0 – EEPROM programming is completed
1 – EEPROM is in programming mode
5EELOCK0bPermanently Lock EEPROM Data(5)0 – EEPROM is not locked
1 – EEPROM is permanently locked
4PWDN0bDevice Power Down (overwrites S0/S1/S2 setting; configuration register settings are unchanged)
Note: PWDN cannot be set to 1 in the EEPROM.
0 – device active (PLL1 and all outputs are enabled)
1 – device power down (PLL1 in power down and all outputs in 3-state)
3:2INCLK00bInput clock selection:00 – Xtal  01 – VCXO   10 – LVCMOS  11 – reserved
1:0SLAVE_ADR00bProgrammable Address Bits A0 and A1 of the Slave Receiver Address
02h7M11bClock source selection for output Y1:0 – input clock  1 – PLL1 clock
6SPICON0bOperation mode selection for pin 18/19(6)
0 – serial programming interface SDA (pin 19) and SCL (pin 18)
1 – control pins S1 (pin 19) and S2 (pin 18)
5:4Y1_ST111bY1-State0/1 Definition
3:2Y1_ST001b00 – device power down (all PLLs in power down and all outputs in 3-State)
01 – Y1 disabled to 3-state		10 – Y1 disabled to low
11 – Y1 enabled
1:0Pdiv1 [9:8]2h10-Bit Y1-Output-Divider Pdiv1:0 – divider reset and stand-by
1-to-1023 – divider value
03h7:0Pdiv1 [7:0]
04h7Y1_70bY1_ST0/Y1_ST1 State Selection(7)
6Y1_60b0 – State0 (predefined by Y1_ST0)
1 – State1 (predefined by Y1_ST1)
5Y1_50b
4Y1_40b
3Y1_30b
2Y1_20b
1Y1_11b
0Y1_00b
05h7:3XCSEL0AhCrystal Load Capacitor Selection(8)00h → 0 pF
01h → 1 pF
02h → 2 pF
:
14h-to-1Fh → 20 pF
2:00bReserved – do not write other than 0
06h7:1BCOUNT40h7-Bit Byte Count (defines the number of bytes which is sent from this device at the next Block Read transfer); all bytes have to be read out to correctly finish the read cycle.)
0EEWRITE0bInitiate EEPROM Write Cycle(4) (9)0– no EEPROM write cycle
1 – start EEPROM write cycle (internal configuration register is saved to the EEPROM)
07h-0Fh—0hUnused address range
(1) Writing data beyond ‘40h’ can affect device function.
(2) All data transferred with the MSB first.
(3) Unless customer-specific setting.
(4) During EEPROM programming, no data is allowed to be sent to the device through the SDA/SCL bus until the programming sequence is completed. However, data can be read out during the programming sequence (Byte Read or Block Read).
(5) If this bit is set to high in the EEPROM, the actual data in the EEPROM is permanently locked. There is no further programming possible. However, data can still be written through the SDA/SCL bus to the internal register to change device function on the fly. New data can no longer be saved to the EEPROM. EELOCK is effective only if written into the EEPROM.
(6) Selection of control pins is effective only if written into the EEPROM. Once written into the EEPROM, the serial programming pins are no longer available. However, if VDDOUT is forced to GND, the two control pins, S1 and S2, temporally act as serial programming pins (SDA/SCL), and the two slave receiver address bits are reset to A0 = 0 and A1 = 0.
(7) These are the bits of the Control Terminal Register. The user can predefine up to eight different control settings. These settings then can be selected by the external control pins, S0, S1, and S2.
(8) The internal load capacitor (C1, C2) has to be used to achieve the best clock performance. External capacitors must be used only to finely adjust CL by a few pFs. The value of CL can be programmed with a resolution of 1 pF for a crystal load range of 0 pF to 20 pF. For CL > 20 pF, use additional external capacitors. Also, the value of the device input capacitance has to be considered which always adds 1.5 pF (6 pF//2 pF) to the selected CL. For more information about VCXO configuration and crystal recommendation, see VCXO Application Guideline for CDCE(L)9xx Family (SCAA085).
(9) Note: The EEPROM WRITE bit must be sent last. This verifies that the content of all internal registers are stored in the EEPROM. The EEWRITE cycle is initiated with the rising edge of the EEWRITE bit. A static level high does not trigger an EEPROM WRITE cycle. The EEWRITE bit has to be reset to low after the programming is completed. The programming status can be monitored by reading out EEPIP. If EELOCK is set to high, no EEPROM programming is possible.
Table 8-4 PLL1 Configuration Register
OFFSET(1) BIT(2) ACRONYM DEFAULT(3) DESCRIPTION
10h 7:5 SSC1_7 [2:0] 000b SSC1: PLL1 SSC Selection (Modulation Amount)(4)
4:2 SSC1_6 [2:0] 000b Down
000 (off)
001 – 0.25%
010 – 0.5%
011 – 0.75%
100 – 1.0%
101 – 1.25%
110 – 1.5%
111 – 2.0%		 Center
000 (off)
001 ± 0.25%
010 ± 0.5%
011 ± 0.75%
100 ± 1.0%
101 ± 1.25%
110 ± 1.5%
111 ± 2.0%
1:0 SSC1_5 [2:1] 000b
11h 7 SSC1_5 [0]
6:4 SSC1_4 [2:0] 000b
3:1 SSC1_3 [2:0] 000b
0 SSC1_2 [2] 000b
12h 7:6 SSC1_2 [1:0]
5:3 SSC1_1 [2:0] 000b
2:0 SSC1_0 [2:0] 000b
13h 7 FS1_7 0b FS1_x: PLL1 Frequency Selection(4)
6 FS1_6 0b 0 – fVCO1_0 (predefined by PLL1_0 – Multiplier/Divider value)
1 – fVCO1_1 (predefined by PLL1_1 – Multiplier/Divider value)
5 FS1_5 0b
4 FS1_4 0b
3 FS1_3 0b
2 FS1_2 0b
1 FS1_1 0b
0 FS1_0 0b
14h 7 MUX1 0b PLL1 Multiplexer: 0 – PLL1
1 – PLL1 Bypass (PLL1 is in power down)
6 M2 1b Output Y2 Multiplexer: 0 – Pdiv1
1 – Pdiv2
5:4 M3 10b Output Y3 Multiplexer: 00 – Pdiv1-Divider
01 – Pdiv2-Divider
10 – Pdiv3-Divider
11 – reserved
3:2 Y2Y3_ST1 11b Y2, Y3-State0/1definition: 00 – Y2/Y3 disabled to 3-State (PLL1 is in power down)
01 – Y2/Y3 disabled to 3-State
10–Y2/Y3 disabled to low
11 – Y2/Y3 enabled
1:0 Y2Y3_ST0 01b
15h 7 Y2Y3_7 0b Y2Y3_x Output State Selection(4)
6 Y2Y3_6 0b 0 – state0 (predefined by Y2Y3_ST0)
1 – state1 (predefined by Y2Y3_ST1)
5 Y2Y3_5 0b
4 Y2Y3_4 0b
3 Y2Y3_3 0b
2 Y2Y3_2 0b
1 Y2Y3_1 1b
0 Y2Y3_0 0b
16h 7 SSC1DC 0b PLL1 SSC down/center selection: 0 – down    1 – center
6:0 Pdiv2 08h 7-Bit Y2-Output-Divider Pdiv2: 0 – reset and stand-by   1-to-127 is divider value
17h 7 — 0b Reserved – do not write others than 0
6:0 Pdiv3 04h 7-Bit Y3-Output-Divider Pdiv3: 0 – reset and stand-by    1-to-127 is divider value
18h 7:0 PLL1_0N [11:4] E10h PLL1_0(5): 30-Bit Multiplier/Divider value for frequency fVCO1_0
(for more information, see PLL Frequency Planning).
19h 7:4 PLL1_0N [3:0]
3:0 PLL1_0R [8:5] 132h
1Ah 7:3 PLL1_0R[4:0]
2:0 PLL1_0Q [5:3] 1Dh
1Bh 7:5 PLL1_0Q [2:0]
4:2 PLL1_0P [2:0] 010b
1:0 VCO1_0_RANGE 11b fVCO1_0 range selection: 00 – fVCO1_0 < 125 MHz
01 – 125 MHz ≤ fVCO1_0 < 150 MHz
10 – 150 MHz ≤ fVCO1_0 < 175 MHz
11 – fVCO1_0 ≥ 175 MHz
1Ch 7:0 PLL1_1N [11:4] E10h PLL1_1(5): 30-Bit Multiplier/Divider value for frequency fVCO1_1
(for more information see PLL Frequency Planning).
1Dh 7:4 PLL1_1N [3:0]
3:0 PLL1_1R [8:5] 132h
1Eh 7:3 PLL1_1R[4:0]
2:0 PLL1_1Q [5:3] 1Dh
1Fh 7:5 PLL1_1Q [2:0]
4:2 PLL1_1P [2:0] 010b
1:0 VCO1_1_RANGE 00b fVCO1_1 range selection: 00 – fVCO1_1 < 125 MHz
01 – 125 MHz ≤ fVCO1_1 < 150 MHz
10 – 150 MHz ≤ fVCO1_1 < 175 MHz
11 – fVCO1_1 ≥ 175 MHz
(1) Writing data beyond 40h can adversely affect device function.
(2) All data is transferred MSB-first.
(3) Unless a custom setting is used.
(4) The user can predefine up to eight different control settings. In normal device operation, these settings can be selected by the external control pins, S0, S1, and S2.
(5) PLL settings limits: 16 ≤ q ≤ 63, 0 ≤ p ≤ 7, 0 ≤ r ≤ 511, 0 < N < 4096.
Table 8-5 PLL2 Configuration Register
OFFSET(1) BIT(2) ACRONYM DEFAULT(3) DESCRIPTION
20h 7:5 SSC2_7 [2:0] 000b SSC2: PLL2 SSC Selection (Modulation Amount)(4)
4:2 SSC2_6 [2:0] 000b Down
000 (off)
001 – 0.25%
010 – 0.5%
011 – 0.75%
100 – 1.0%
101 – 1.25%
110 – 1.5%
111 – 2.0%		 Center
000 (off)
001 ± 0.25%
010 ± 0.5%
011 ± 0.75%
100 ± 1.0%
101 ± 1.25%
110 ± 1.5%
111 ± 2.0%
1:0 SSC2_5 [2:1] 000b
21h 7 SSC2_5 [0]
6:4 SSC2_4 [2:0] 000b
3:1 SSC2_3 [2:0] 000b
0 SSC2_2 [2] 000b
22h 7:6 SSC2_2 [1:0]
5:3 SSC2_1 [2:0] 000b
2:0 SSC2_0 [2:0] 000b
23h 7 FS2_7 0b FS2_x: PLL2 Frequency Selection(4)
6 FS2_6 0b 0 – fVCO2_0 (predefined by PLL2_0 – Multiplier/Divider value)
1 – fVCO2_1 (predefined by PLL2_1 – Multiplier/Divider value)
5 FS2_5 0b
4 FS2_4 0b
3 FS2_3 0b
2 FS2_2 0b
1 FS2_1 0b
0 FS2_0 0b
24h 7 MUX2 0b PLL2 Multiplexer: 0 – PLL2
1 – PLL2 Bypass (PLL2 is in power down)
6 M4 1b Output Y4 Multiplexer: 0 – Pdiv2
1 – Pdiv4
5:4 M5 10b Output Y5 Multiplexer: 00 – Pdiv2-Divider
01 – Pdiv4-Divider
10 – Pdiv5-Divider
11 – reserved
3:2 Y4Y5_ST1 11b Y4, Y5-State0/1definition: 00 – Y4/Y5 disabled to 3-State (PLL2 is in power down)
01 – Y4/Y5 disabled to 3-State
10–Y4/Y5 disabled to low
11 – Y4/Y5 enabled
1:0 Y4Y5_ST0 01b
25h 7 Y4Y5_7 0b Y4Y5_x Output State Selection(4)
6 Y4Y5_6 0b 0 – state0 (predefined by Y4Y5_ST0)
1 – state1 (predefined by Y4Y5_ST1)
5 Y4Y5_5 0b
4 Y4Y5_4 0b
3 Y4Y5_3 0b
2 Y4Y5_2 0b
1 Y4Y5_1 1b
0 Y4Y5_0 0b
26h 7 SSC2DC 0b PLL2 SSC down/center selection: 0 – down
1 – center
6:0 Pdiv4 05h 7-Bit Y4-Output-Divider Pdiv4: 0 – reset and stand-by   1-to-127 – divider value
27h 7 — 0b Reserved – do not write others than 0
6:0 Pdiv5 05h 7-Bit Y5-Output-Divider Pdiv5: 0 – reset and stand-by    1-to-127 – divider value
28h 7:0 PLL2_0N [11:4 E58h PLL2_0(5): 30-Bit Multiplier/Divider value for frequency fVCO2_0
(for more information see PLL Frequency Planning).
29h 7:4 PLL2_0N [3:0]
3:0 PLL2_0R [8:5] 198h
2Ah 7:3 PLL2_0R[4:0]
2:0 PLL2_0Q [5:3] 1Ch
2Bh 7:5 PLL2_0Q [2:0]
4:2 PLL2_0P [2:0] 010b
1:0 VCO2_0_RANGE 11b fVCO2_0 range selection: 00 – fVCO2_0 < 125 MHz
01 – 125 MHz ≤ fVCO2_0 < 150 MHz
10 – 150 MHz ≤ fVCO2_0 < 175 MHz
11 – fVCO2_0 ≥ 175 MHz
2Ch 7:0 PLL2_1N [11:4] E58h PLL2_1(5): 30-Bit Multiplier/Divider value for frequency fVCO2_1
(for more information see PLL Frequency Planning).
2Dh 7:4 PLL2_1N [3:0]
3:0 PLL2_1R [8:5] 198h
2Eh 7:3 PLL2_1R[4:0]
2:0 PLL2_1Q [5:3] 1Ch
2Fh 7:5 PLL2_1Q [2:0]
4:2 PLL2_1P [2:0] 010b
1:0 VCO2_1_RANGE 00b fVCO2_1 range selection: 00 – fVCO2_1 < 125 MHz
01 – 125 MHz ≤ fVCO2_1 < 150 MHz
10 – 150 MHz ≤ fVCO2_1 < 175 MHz
11 – fVCO2_1 ≥ 175 MHz
(1) Writing data beyond 40h can adversely affect device function.
(2) All data is transferred MSB-first.
(3) Unless a custom setting is used.
(4) The user can predefine up to eight different control settings. In normal device operation, these settings can be selected by the external control pins, S0, S1, and S2.
(5) PLL settings limits: 16 ≤ q ≤ 63, 0 ≤ p ≤ 7, 0 ≤ r ≤ 511, 0 < N < 4096.
Table 8-6 PLL3 Configuration Register
OFFSET(1) BIT(2) ACRONYM DEFAULT(3) DESCRIPTION
30h 7:5 SSC3_7 [2:0] 000b SSC3: PLL3 SSC Selection (Modulation Amount)(4)
4:2 SSC3_6 [2:0] 000b Down
000 (off)
001 – 0.25%
010 – 0.5%
011 – 0.75%
100 – 1.0%
101 – 1.25%
110 – 1.5%
111 – 2.0%		 Center
000 (off)
001 ± 0.25%
010 ± 0.5%
011 ± 0.75%
100 ± 1.0%
101 ± 1.25%
110 ± 1.5%
111 ± 2.0%
1:0 SSC3_5 [2:1] 000b
31h 7 SSC3_5 [0]
6:4 SSC3_4 [2:0] 000b
3:1 SSC3_3 [2:0] 000b
0 SSC3_2 [2] 000b
32h 7:6 SSC3_2 [1:0]
5:3 SSC3_1 [2:0] 000b
2:0 SSC3_0 [2:0] 000b
33h 7 FS3_7 0b FS3_x: PLL3 Frequency Selection(4)
6 FS3_6 0b 0 – fVCO3_0 (predefined by PLL3_0 – Multiplier/Divider value)
1 – fVCO3_1 (predefined by PLL3_1 – Multiplier/Divider value)
5 FS3_5 0b
4 FS3_4 0b
3 FS3_3 0b
2 FS3_2 0b
1 FS3_1 0b
0 FS3_0 0b
34h 7 MUX3 0b PLL3 Multiplexer: 0 – PLL3
1 – PLL3 Bypass (PLL3 is in power down)
6 M6 1b Output Y6 Multiplexer: 0 – Pdiv4
1 – Pdiv6
5:4 M7 10b Output Y7 Multiplexer: 00 – Pdiv4-Divider
01 – Pdiv6-Divider
10 – Pdiv7-Divider
11 – reserved
3:2 Y6Y7_ST1 11b Y6, Y7-State0/1definition: 00 – Y6/Y7 disabled to 3-State and PLL3 power down
01 – Y6/Y7 disabled to 3-State
10 –Y6/Y7 disabled to low
11 – Y6/Y7 enabled
1:0 Y6Y7_ST0 01b
35h 7 Y6Y7_7 0b Y6Y7_x Output State Selection(4)
6 Y6Y7_6 0b 0 – state0 (predefined by Y6Y7_ST0)
1 – state1 (predefined by Y6Y7_ST1)
5 Y6Y7_5 0b
4 Y6Y7_4 0b
3 Y6Y7_3 0b
2 Y6Y7_2 0b
1 Y6Y7_1 1b
0 Y6Y7_0 0b
36h 7 SSC3DC 0b PLL3 SSC down/center selection: 0 – down  1 – center
6:0 Pdiv6 09h 7-Bit Y6-Output-Divider Pdiv6: 0 – reset and stand-by   1-to-127 – divider value
37h 7 — 0b Reserved – do not write others than 0
6:0 Pdiv7 04h 7-Bit Y7-Output-Divider Pdiv7: 0 – reset and stand-by   1-to-127 – divider value
38h 7:0 PLL3_0N [11:4] FF8h PLL3_0(5): 30-Bit Multiplier/Divider value for frequency fVCO3_0
(for more information, see PLL Frequency Planning).
39h 7:4 PLL3_0N [3:0]
3:0 PLL3_0R [8:5] 000h
3Ah 7:3 PLL3_0R[4:0]
2:0 PLL3_0Q [5:3] 10h
3Bh 7:5 PLL3_0Q [2:0]
4:2 PLL3_0P [2:0] 001b
1:0 VCO3_0_RANGE 11b fVCO3_0 range selection: 00 – fVCO3_0 < 125 MHz
01 – 125 MHz ≤ fVCO3_0 < 150 MHz
10 – 150 MHz ≤ fVCO3_0 < 175 MHz
11 – fVCO3_0 ≥ 175 MHz
3Ch 7:0 PLL3_1N [11:4] FF8h PLL3_1(5): 30-Bit Multiplier/Divider value for frequency fVCO3_1
(for more information, see PLL Frequency Planning).
3Dh 7:4 PLL3_1N [3:0]
3:0 PLL3_1R [8:5] 000h
3Eh 7:3 PLL3_1R[4:0]
2:0 PLL3_1Q [5:3] 10h
3Fh 7:5 PLL3_1Q [2:0]
4:2 PLL3_1P [2:0] 001b
1:0 VCO3_1_RANGE 00b fVCO3_1 range selection: 00 – fVCO3_1 < 125 MHz
01 – 125 MHz ≤ fVCO3_1 < 150 MHz
10 – 150 MHz ≤ fVCO3_1 < 175 MHz
11 – fVCO3_1 ≥ 175 MHz
(1) Writing data beyond 40h can affect device function.
(2) All data is transferred MSB-first.
(3) Unless a custom setting is used.
(4) These are the bits of the Control Terminal Register. The user can pre-define up to eight different control settings. At normal device operation, these setting can be selected by the external control pins, S0, S1, and S2.
(5) PLL settings limits: 16 ≤ q ≤ 63, 0 ≤ p ≤ 7, 0 ≤ r ≤ 511, 0 < N < 4096.