SLAS564I August   2007  – December 2024 CDCE937 , CDCEL937

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements: CLK_IN
    7. 5.7 Timing Requirements: SDA/SCL
    8. 5.8 EEPROM Specification
    9. 5.9 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Control Terminal Setting
      2. 7.3.2 Default Device Setting
      3. 7.3.3 SDA/SCL Serial Interface
      4. 7.3.4 Data Protocol
    4. 7.4 Device Functional Modes
      1. 7.4.1 SDA/SCL Hardware Interface
    5. 7.5 Programming
  9. 8 Register Maps
    1. 8.1 SDA/SCL Configuration Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Spread Spectrum Clock (SSC)
        2. 9.2.2.2 PLL Frequency Planning
        3. 9.2.2.3 Crystal Oscillator Start-Up
        4. 9.2.2.4 Frequency Adjustment With Crystal Oscillator Pulling
        5. 9.2.2.5 Unused Inputs and Outputs
        6. 9.2.2.6 Switching Between XO and VCXO Mode
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
      2. 10.1.2 Development Support
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

7.1 Overview

The CDCE937 and CDCEL937 devices are modular PLL-based, low-cost, high-performance, programmable clock synthesizers, multipliers, and dividers. The devices generate up to seven output clocks from a single input frequency. Each output can be programmed in-system for any clock frequency up to 230MHz, using one of the three integrated configurable PLLs. The CDCx937 has separate output supply pins, VDDOUT, which is 1.8V for CDCEL937 and 2.5V to 3.3V for CDCE937.

The input accepts an external crystal or LVCMOS clock signal. If an external crystal is used, an on-chip load capacitor is adequate for most applications. The value of the load capacitor is programmable from 0pF to 20pF.

Additionally, a selectable on-chip VCXO allows synchronization of the output frequency to an external control signal, that is, the PWM signal.

The deep M/N divider ratio allows the generation of 0ppm audio/video, networking (WLAN, BlueTooth, Ethernet, GPS) or Interface (USB, IEEE1394, Memory Stick) clocks from a reference input frequency such as 27MHz.

All PLLs supports SSC (Spread-Spectrum Clocking). SSC can be Center-Spread or Down-Spread clocking which is a common technique to reduce electro-magnetic interference (EMI).

Based on the PLL frequency and the divider settings, the internal loop filter components are automatically adjusted to achieve high stability and optimized jitter transfer characteristic of each PLL.

The device supports non-volatile EEPROM programming for ease-customized application. The device is preset to a factory default configuration (see Default Device Setting). The device can be reprogrammed to a different application configuration before PCB assembly, or reprogrammed by in-system programming. All device settings are programmable through SDA/SCL bus, a 2-wire serial interface.

Three programmable control inputs, S0, S1 and S2, can be used to control various aspects of operation including frequency selection changing the SSC parameters to lower EMI, PLL bypass, power down, and choosing between low level or 3-state for output-disable function.

The CDCx937 operates in a 1.8V environment. The CDCx937 is characterized for operation from –40°C to 85°C.