SLAS715D June   2010  – October 2024 TLV320AIC3104-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Switching Characteristics I2S/LJF/RJF Timing in Master Mode
    7. 6.7  Switching Characteristics I2S/LJF/RJF Timing in Slave Mode
    8. 6.8  Switching Characteristics DSP Timing in Master Mode
    9. 6.9  Switching Characteristics DSP Timing in Slave Mode
    10. 6.10 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Audio Data Converters
      2. 7.3.2  Stereo Audio ADC
        1. 7.3.2.1 Stereo Audio ADC High-Pass Filter
      3. 7.3.3  Automatic Gain Control (AGC)
      4. 7.3.4  Stereo Audio DAC
      5. 7.3.5  Digital Audio Processing for Playback
      6. 7.3.6  Digital Interpolation Filter
      7. 7.3.7  Delta-Sigma Audio DAC
      8. 7.3.8  Audio DAC Digital Volume Control
      9. 7.3.9  Analog Output Common-mode Adjustment
      10. 7.3.10 Audio DAC Power Control
      11. 7.3.11 Audio Analog Inputs
      12. 7.3.12 Analog Input Bypass Path Functionality
      13. 7.3.13 ADC PGA Signal Bypass Path Functionality
      14. 7.3.14 Input Impedance and VCM Control
      15. 7.3.15 MICBIAS Generation
      16. 7.3.16 Analog Fully Differential Line Output Drivers
      17. 7.3.17 Analog High-Power Output Drivers
      18. 7.3.18 Short-Circuit Output Protection
      19. 7.3.19 Jack and Headset Detection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Digital Audio Processing for Record Path
      2. 7.4.2 Increasing DAC Dynamic Range
      3. 7.4.3 Passive Analog Bypass During Power Down
      4. 7.4.4 Hardware Reset
    5. 7.5 Programming
      1. 7.5.1  Digital Control Serial Interface
      2. 7.5.2  I2C Control Interface
      3. 7.5.3  I2C Bus Debug in a Glitched System
      4. 7.5.4  Digital Audio Data Serial Interface
      5. 7.5.5  Right-Justified Mode
      6. 7.5.6  Left-Justified Mode
      7. 7.5.7  I2S Mode
      8. 7.5.8  DSP Mode
      9. 7.5.9  TDM Data Transfer
      10. 7.5.10 Audio Clock Generation
  9. 8 Register Maps
    1. 8.1 Output Stage Volume Controls
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 External Speaker Driver in Infotainment and Cluster Applications
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 External Speaker Amplifier With Separate Line Outputs
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Device Nomenclature
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Community Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

6.5 Electrical Characteristics

at 25°C, AVDD = DRVDD = IOVDD = 3.3 V, DVDD = 1.8 V, fS = 48 kHz, and 16-bit audio data (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
AUDIO ADC
Input signal level Single-ended configurations 0.707 VRMS
SNR Signal-to-noise ratio(1)(2) A-weighted, fS = 48 kSPS, 0-dB PGA gain,
inputs ac-shorted to ground		 80 92 dB
DR Dynamic range(1)(2) fS = 48 kSPS; 0-dB PGA gain; 1-kHz, –60-dB,
full-scale input signal		 93 dB
THD Total harmonic distortion fS = 48 kSPS; 0-dB PGA gain; 1-kHz, –2-dB,
full-scale input signal		 –89 –75 dB
PSRR Power-supply rejection ratio 217-Hz signal applied to DRVDD 55 dB
1-kHz signal applied to DRVDD 44
Input channel separation 1-kHz, –2-dB, full-scale signal, MIC1 to MIC2 –71 dB
Gain error fS = 48 kSPS; 0-dB PGA gain; 1-kHz, –2-dB,
full-scale input signal		 0.82 dB
ADC programmable-gain amplifier maximum gain 1-kHz input tone 59.5 dB
ADC programmable-gain amplifier step size 0.5 dB
Input resistance MIC1L/MIC1R inputs routed to single ADC
input MIX attenuation = 0 dB		 20 kΩ
MIC1L/MIC1R inputs routed to single ADC
input MIX attenuation = 12 dB		 80
MIC2L/MIC2R inputs routed to single ADC
input MIX attenuation = 0 dB		 20
MIC2L/MIC2R inputs routed to single ADC
input MIX attenuation = 12 dB		 80
Input resistance 80 kΩ
Input capacitance MIC1/LINE1 inputs 10 pF
Input level control minimum attenuation setting 0 dB
Input level control maximum attenuation setting 12 dB
Input level control attenuation step size 1.5 dB
ANALOG PASSTHROUGH MODE
RDS(on) Input-to-output switch resistance MIC1/LINE1 to LINEOUT 330 Ω
MIC2/LINE2 to LINEOUT 330
INPUT SIGNAL LEVEL, DIFFERENTIAL
SNR Signal-to-noise ratio A-weighted, fS = 48 kSPS, 0-dB PGA gain,
inputs ac-shorted to ground		 92 dB
THD Total harmonic distortion fS = 48 kHz; 0-dB PGA gain, 1-kHz, –2-dB,
full-scale input signal		 –94 dB
ADC DIGITAL DECIMATION FILTER (fS = 48 kHz)
Filter gain From 0 fS to 0.39 fS ±0.1 dB
At 0.4125 fS –0.25
At 0.45 fS –3
At 0.5 fS –17.5
From 0.55 fS to 64 fS –75
Filter group delay 17/fS s
MICROPHONE BIAS
Bias voltage Programmable setting = 2 V 2 V
Programmable setting = 2.5 V 2.3 2.455 2.7
Programmable setting = DRVDD DRVDD - 0.24
Current sourcing Programmable setting = 2.5 V 4 mA
AUDIO DAC, DIFFERENTIAL LINE OUTPUT (RLOAD = 10 kΩ)
Full-scale output voltage 0-dB input full-scale signal, output common-mode setting = 1.35 V, output volume control = 0 dB 1.414 VRMS
4 VPP
Signal-to-noise ratio(3) A-weighted, fS = 48 kHz, output volume control = 0 dB, no input signal, referenced to full-scale input level 90 102 dB
Dynamic range A-weighted, fS = 48 kHz, –60-dB input full-scale signal, output volume control = 0 dB, output common-mode setting = 1.35 V 97 dB
Total harmonic distortion fS = 48 kHz; 0-dB, 1-kHz input full-scale signal; output volume control = 0 dB; output common-mode setting = 1.35 V –95 –75 dB
PSRR Power-supply rejection ratio 217-Hz signal applied to DRVDD, AVDD_DAC 78 dB
1-kHz signal applied to DRVDD, AVDD_DAC 80
DAC channel separation 0-dB full-scale input signal between left and right lineout 86 dB
DAC interchannel gain mismatch 1-kHz input, 0-dB gain 0.1 dB
DAC gain error 0-dB, 1-kHz input full-scale signal; output volume control = 0 dB; output common-mode setting = 1.35 V; fS = 48 kHz –0.2 dB
AUDIO DAC, SINGLE-ENDED LINE OUTPUT (RLOAD = 10 kΩ)
Full-scale output voltage 0-dB input full-scale signal, output common-mode setting = 1.35 V, output volume control = 0 dB 0.707 VRMS
SNR Signal-to-noise ratio A-weighted, fS = 48 kHz, output volume control = 0 dB, no input signal, output common-mode setting = 1.35 V 97 dB
THD Total harmonic distortion

fS = 48 kHz; 0-dB, 1-kHz input full-scale signal;

output volume control = 0 dB;

output common-mode setting = 1.35 V

 -84 dB
DAC gain error 0-dB, 1-kHz input full-scale signal; output volume control = 0 dB; output common-mode setting = 1.35 V; fS = 48 kHz 0.55 dB
AUDIO DAC, SINGLE-ENDED HEADPHONE OUTPUT (RLOAD = 16 Ω)
Full-scale output voltage 0-dB input full-scale signal, output common-mode setting = 1.35 V, output volume control = 0 dB 0.707 VRMS
SNR Signal-to-noise ratio A-weighted, fS = 48 kHz, output volume control = 0 dB, no input signal, referenced to full-scale input level 96 dB
A-weighted, fS = 48 kHz, output volume control = 0 dB, no input signal, referenced to full-scale input level, 50% DAC current-boost mode 97
Dynamic range A-weighted, fS = 48 kHz, –60-dB input full-scale signal, output volume control = 0 dB, output common-mode setting = 1.35 V 91 dB
THD Total harmonic distortion fS = 48 kHz, 0-dB input full-scale signal, output volume control = 0 dB, output common-mode setting = 1.35 V –71 –65 dB
PSRR Power-supply rejection ratio 217-Hz signal applied to DRVDD, AVDD_DAC 43 dB
1-kHz signal applied to DRVDD, AVDD_DAC 41
DAC channel seperation Right headphone out 89 dB
DAC gain error 0-dB, 1-kHz input full-scale signal; output volume control = 0 dB; output common-mode setting = 1.35 V; fS = 48 kHz –0.85 dB
DAC DIGITAL INTERPOLATION FILTER (fS = 48 kHz)
Pass band 0 0.45 fS Hz
Pass-band ripple ±0.06 dB
Transition band 0.45 fS 0.55 fS Hz
Stop band 0.55 fS 7.5 fS Hz
Stop-band attenuation 65 dB
Group delay 21 / fS s
STEREO HEADPHONE DRIVER (AC-Coupled Output Configuration(3))
0-dB full-scale output voltage 0-dB gain to high-power outputs, output common-mode voltage setting = 1.35 V 0.707 VRMS
Programmable output common-mode voltage (applicable to line outputs also) First option 1.35 V
Second option 1.5
Third option 1.65
Fourth option 1.8
Maximum programmable output level control gain 9 dB
Programmable output level control gain step size 1 dB
PO Maximum output power RL = 32 Ω 15 mW
RL = 16 Ω 30
SNR Signal-to-noise ratio(4) A-weighted 94 dB
THD Total harmonic distortion 1-kHz output, PO = 5 mW, RL = 32 Ω –77 dB%
0.014
1-kHz output, PO = 10 mW, RL = 32 Ω –76
0.016
1-kHz output, PO = 10 mW, RL = 16 Ω –73
0.022
1-kHz output, PO = 20 mW, RL = 16 Ω –71
0.028
Channel separation 1-kHz, 0-dB input 90 dB
PSRR Power-supply rejection ratio 217 Hz, 100 mVPP on AVDD, DRVDD1/2 48 dB
Mute attenuation 1-kHz output 107 dB
DIGITAL I/O
VIL Input low level –0.3 0.3 IOVDD V
VIH Input high level(5) IOVDD > 1.6 V 0.7 IOVDD V
IOVDD ≤ 1.6 V 1.1
VOL Output low level 0.1 IOVDD V
VOH Output high level 0.8 IOVDD V
CURRENT CONSUMPTION (DRVDD = AVDD = IOVDD = 3.3 V, DVDD = 1.8 V)
IIN IDRVDD + IAVDD_DAC RESET held low 0.1 µA
IDVDD 0.2
IDRVDD + IAVDD_DAC Mono ADC record, fS = 8 kSPS, I2S slave,
AGC off, no signal		 2.15 mA
IDVDD 0.48
IDRVDD + IAVDD_DAC

Stereo ADC record, fS = 8 ksps, I2S slave, AGC off,

no signal

 4.1
IDVDD 0.62
IDRVDD + IAVDD_DAC Stereo ADC record, fS = 48 kSPS, I2S slave,
AGC off, no signal		 4.31(6)
IDVDD 2.45(6)
IDRVDD + IAVDD_DAC Stereo DAC playback to lineout, analog mixer bypassed, fS = 48 kSPS, I2S slave 3.5
IDVDD 2.3
IDRVDD + IAVDD_DAC Stereo DAC playback to lineout, fS = 48 kSPS,
I2S slave, no signal		 4.9
IDVDD 2.3
IDRVDD + IAVDD_DAC Stereo DAC playback to mono single-ended headphone, fS = 48 kSPS, I2S slave, no signal 6.7
IDVDD 2.3
IDRVDD + IAVDD_DAC Stereo line in to mono line out, no signal 3.11
IDVDD 0
IDRVDD + IAVDD_DAC Extra power when PLL enabled 1.4
IDVDD 0.9
IDRVDD + IAVDD_DAC All blocks powered down, headset detection enabled, headset not inserted 28 µA
IDVDD 2
(1) Ratio of output level with 1-kHz, full-scale, sine-wave input to the output level with the inputs short-circuited, measured A-weighted over a 20-Hz to 20-kHz bandwidth using an audio analyzer.
(2) All performance measurements done with 20-kHz, low-pass filter and an A-weighted filter, where noted. Failure to use such a filter may result in higher THD+N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter removes out-of-band noise, which, although not audible, may affect dynamic specification values.
(3) Unless otherwise noted, all measurements use an output common-mode voltage setting of 1.35 V, a 0-dB output level control gain, and a 16-Ω single-ended load.
(4) Ratio of output level with a 1-kHz, full-scale input to the output level playing an all-zero signal, measured A-weighted over a 20-Hz to
20-kHz bandwidth.
(5) When IOVDD < 1.6 V, minimum VIH is 1.1 V.
(6) Additional power is consumed when the PLL is powered.