SLAS715D
June 2010 – October 2024
TLV320AIC3104-Q1
PRODUCTION DATA
1
1
Features
2
Applications
3
Description
4
Device Comparison
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Switching Characteristics I2S/LJF/RJF Timing in Master Mode
6.7
Switching Characteristics I2S/LJF/RJF Timing in Slave Mode
6.8
Switching Characteristics DSP Timing in Master Mode
6.9
Switching Characteristics DSP Timing in Slave Mode
6.10
Typical Characteristics
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
Audio Data Converters
7.3.2
Stereo Audio ADC
7.3.2.1
Stereo Audio ADC High-Pass Filter
7.3.3
Automatic Gain Control (AGC)
7.3.4
Stereo Audio DAC
7.3.5
Digital Audio Processing for Playback
7.3.6
Digital Interpolation Filter
7.3.7
Delta-Sigma Audio DAC
7.3.8
Audio DAC Digital Volume Control
7.3.9
Analog Output Common-mode Adjustment
7.3.10
Audio DAC Power Control
7.3.11
Audio Analog Inputs
7.3.12
Analog Input Bypass Path Functionality
7.3.13
ADC PGA Signal Bypass Path Functionality
7.3.14
Input Impedance and VCM Control
7.3.15
MICBIAS Generation
7.3.16
Analog Fully Differential Line Output Drivers
7.3.17
Analog High-Power Output Drivers
7.3.18
Short-Circuit Output Protection
7.3.19
Jack and Headset Detection
7.4
Device Functional Modes
7.4.1
Digital Audio Processing for Record Path
7.4.2
Increasing DAC Dynamic Range
7.4.3
Passive Analog Bypass During Power Down
7.4.4
Hardware Reset
7.5
Programming
7.5.1
Digital Control Serial Interface
7.5.2
I2C Control Interface
7.5.3
I2C Bus Debug in a Glitched System
7.5.4
Digital Audio Data Serial Interface
7.5.5
Right-Justified Mode
7.5.6
Left-Justified Mode
7.5.7
I2S Mode
7.5.8
DSP Mode
7.5.9
TDM Data Transfer
7.5.10
Audio Clock Generation
8
Register Maps
8.1
Output Stage Volume Controls
9
Application and Implementation
9.1
Application Information
9.2
Typical Applications
9.2.1
External Speaker Driver in Infotainment and Cluster Applications
9.2.1.1
Design Requirements
9.2.1.2
Detailed Design Procedure
9.2.1.3
Application Curves
9.2.2
External Speaker Amplifier With Separate Line Outputs
9.2.2.1
Design Requirements
9.2.2.2
Detailed Design Procedure
9.3
Power Supply Recommendations
9.4
Layout
9.4.1
Layout Guidelines
9.4.2
Layout Example
10
Device and Documentation Support
10.1
Device Support
10.1.1
Device Nomenclature
10.2
Documentation Support
10.2.1
Related Documentation
10.3
Receiving Notification of Documentation Updates
10.4
Community Resources
10.5
Trademarks
10.6
Electrostatic Discharge Caution
11
Revision History
12
Mechanical, Packaging, and Orderable Information
1
Features
Qualified for Automotive Applications
AEC-Q100 Qualified With the Following Results:
Device Temperature Grade 2: –40°C to 105°C
Ambient Operating Temperature Range
Device HBM ESD Classification Level 2
Device CDM ESD Classification Level C6
Stereo Audio DAC:
102-dBA Signal-to-Noise Ratio
16-, 20-, 24-, or 32-Bit Data
Supports Sample Rates From 8kHz to 96kHz
3D, Bass, Treble, EQ, De-Emphasis Effects
Flexible Power Saving Modes and
Performance are Available
Stereo Audio ADC:
92-dBA Signal-to-Noise Ratio
Supports Sample Rates From 8kHz to 96kHz
Digital Signal Processing and Noise Filtering
available during record
Six Audio Input Pins:
One Stereo Pair of Single-Ended Inputs
One Stereo Pair of Fully Differential Inputs
Six Audio Output Drivers:
Fully Differential or Single-Ended Stereo Headphone Drivers
Fully Differential Stereo Line Outputs
Low Power: 14-mW Stereo, 48kHz Playback With 3.3V Analog Supply
Ultralow-Power Mode With Passive Analog Bypass
Programmable Input/Output Analog Gains
Automatic Gain Control (AGC) for Record
Programmable Microphone Bias Level
Programmable PLL for Flexible Clock Generation
I
2
C Control Bus
Audio Serial Data Bus Supports I
2
S, Left/RightJustified, DSP, and TDM Modes
Extensive Modular Power Control
Power Supplies:
Analog: 2.7V to 3.6V
Digital Core: 1.525V to 1.95V
Digital I/O: 1.1V to 3.6V