SLAS715D June   2010  – October 2024 TLV320AIC3104-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Switching Characteristics I2S/LJF/RJF Timing in Master Mode
    7. 6.7  Switching Characteristics I2S/LJF/RJF Timing in Slave Mode
    8. 6.8  Switching Characteristics DSP Timing in Master Mode
    9. 6.9  Switching Characteristics DSP Timing in Slave Mode
    10. 6.10 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Audio Data Converters
      2. 7.3.2  Stereo Audio ADC
        1. 7.3.2.1 Stereo Audio ADC High-Pass Filter
      3. 7.3.3  Automatic Gain Control (AGC)
      4. 7.3.4  Stereo Audio DAC
      5. 7.3.5  Digital Audio Processing for Playback
      6. 7.3.6  Digital Interpolation Filter
      7. 7.3.7  Delta-Sigma Audio DAC
      8. 7.3.8  Audio DAC Digital Volume Control
      9. 7.3.9  Analog Output Common-mode Adjustment
      10. 7.3.10 Audio DAC Power Control
      11. 7.3.11 Audio Analog Inputs
      12. 7.3.12 Analog Input Bypass Path Functionality
      13. 7.3.13 ADC PGA Signal Bypass Path Functionality
      14. 7.3.14 Input Impedance and VCM Control
      15. 7.3.15 MICBIAS Generation
      16. 7.3.16 Analog Fully Differential Line Output Drivers
      17. 7.3.17 Analog High-Power Output Drivers
      18. 7.3.18 Short-Circuit Output Protection
      19. 7.3.19 Jack and Headset Detection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Digital Audio Processing for Record Path
      2. 7.4.2 Increasing DAC Dynamic Range
      3. 7.4.3 Passive Analog Bypass During Power Down
      4. 7.4.4 Hardware Reset
    5. 7.5 Programming
      1. 7.5.1  Digital Control Serial Interface
      2. 7.5.2  I2C Control Interface
      3. 7.5.3  I2C Bus Debug in a Glitched System
      4. 7.5.4  Digital Audio Data Serial Interface
      5. 7.5.5  Right-Justified Mode
      6. 7.5.6  Left-Justified Mode
      7. 7.5.7  I2S Mode
      8. 7.5.8  DSP Mode
      9. 7.5.9  TDM Data Transfer
      10. 7.5.10 Audio Clock Generation
  9. 8 Register Maps
    1. 8.1 Output Stage Volume Controls
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 External Speaker Driver in Infotainment and Cluster Applications
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 External Speaker Amplifier With Separate Line Outputs
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Device Nomenclature
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Community Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

3 Description

The TLV320AIC3104-Q1 is a low-power stereo audio codec with stereo headphone amplifiers, as well as multiple inputs and outputs that are programmable in single-ended or fully differential configurations. Extensive register-based power control is included, enabling stereo 48kHz DAC playback as low as 14mW from a 3.3V analog supply, making the device an excellent choice for car audio applications in cluster and head unit systems.

The record path of the TLV320AIC3104-Q1 contains integrated microphone bias, digitally controlled stereo microphone preamplifier, and automatic gain control (AGC), with mix/mux capability among the multiple analog inputs. Programmable filters are available during record which can remove audible noise that can occur during noisy and unpredictable environments, such as when an e-call system is activated. The playback path includes mix/mux capability from the stereo DAC and selected inputs, through programmable volume controls, to the various outputs.

The TLV320AIC3104-Q1 contains four high-power output drivers as well as two fully differential output drivers. The high-power output drivers are capable of driving a variety of load configurations, including up to four channels of single-ended 16Ω headphones using AC-coupling capacitors, or stereo 16Ω headphones in a capless output configuration. These parameters enable the TLV320AIC3104-Q1 to act as an interface between the MCU and speaker amplifiers, such as the TPA3111D1-Q1, in various audio applications in the infotainment and cluster fields.

The stereo audio DAC supports sampling rates from 8kHz to 96kHz and includes programmable digital filtering in the DAC path for 3D, bass, treble, midrange effects, speaker equalization, and de-emphasis for 32kHz, 44.1kHz, and 48kHz sample rates. The stereo audio ADC supports sampling rates from 8kHz to 96kHz and is preceded by programmable gain amplifiers (PGA) or an automatic gain control (AGC) circuit that can provide up to 59.5dB analog gain for low-level microphone inputs. The TLV320AIC3104-Q1 provides an extremely high range of programmability for both attack (8ms to 1,408ms) and for decay (0.05s to 22.4s). This extended AGC range allows the AGC to be tuned for many types of applications.

Where neither analog nor digital signal processing are required, the device can be put in a special analog signal passthrough mode. This mode significantly reduces power consumption, as most of the device is powered down during this passthrough operation.

The serial control bus supports the I2C protocol, whereas the serial audio data bus is programmable for I2S, left/right-justified, DSP, or TDM modes. A highly programmable PLL is included for flexible clock generation and support for all standard audio rates from a wide range of available MCLKs, varying from 512kHz to 50MHz, with special attention paid to the most-popular cases of 12MHz, 13MHz, 16MHz, 19.2MHz, and 19.68MHz system clocks.

The TLV320AIC3104-Q1 operates from an analog supply of 2.7V to 3.6V, a digital core supply of 1.525V to 1.95V, and a digital I/O supply of 1.1V to 3.6V.

Device Information
PART NUMBER PACKAGE(1) PACKAGE SIZE(2)
TLV320AIC3104-Q1 VQFN (32) 5.00mm × 5.00mm
(1) For all available packages, see the orderable addendum at the end of the datasheet.
(2) The package size (length × width) is a nominal value and includes pins, where applicable.
TLV320AIC3104-Q1 Simplified Diagram Simplified Diagram