SLAS715D June   2010  – October 2024 TLV320AIC3104-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Switching Characteristics I2S/LJF/RJF Timing in Master Mode
    7. 6.7  Switching Characteristics I2S/LJF/RJF Timing in Slave Mode
    8. 6.8  Switching Characteristics DSP Timing in Master Mode
    9. 6.9  Switching Characteristics DSP Timing in Slave Mode
    10. 6.10 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Audio Data Converters
      2. 7.3.2  Stereo Audio ADC
        1. 7.3.2.1 Stereo Audio ADC High-Pass Filter
      3. 7.3.3  Automatic Gain Control (AGC)
      4. 7.3.4  Stereo Audio DAC
      5. 7.3.5  Digital Audio Processing for Playback
      6. 7.3.6  Digital Interpolation Filter
      7. 7.3.7  Delta-Sigma Audio DAC
      8. 7.3.8  Audio DAC Digital Volume Control
      9. 7.3.9  Analog Output Common-mode Adjustment
      10. 7.3.10 Audio DAC Power Control
      11. 7.3.11 Audio Analog Inputs
      12. 7.3.12 Analog Input Bypass Path Functionality
      13. 7.3.13 ADC PGA Signal Bypass Path Functionality
      14. 7.3.14 Input Impedance and VCM Control
      15. 7.3.15 MICBIAS Generation
      16. 7.3.16 Analog Fully Differential Line Output Drivers
      17. 7.3.17 Analog High-Power Output Drivers
      18. 7.3.18 Short-Circuit Output Protection
      19. 7.3.19 Jack and Headset Detection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Digital Audio Processing for Record Path
      2. 7.4.2 Increasing DAC Dynamic Range
      3. 7.4.3 Passive Analog Bypass During Power Down
      4. 7.4.4 Hardware Reset
    5. 7.5 Programming
      1. 7.5.1  Digital Control Serial Interface
      2. 7.5.2  I2C Control Interface
      3. 7.5.3  I2C Bus Debug in a Glitched System
      4. 7.5.4  Digital Audio Data Serial Interface
      5. 7.5.5  Right-Justified Mode
      6. 7.5.6  Left-Justified Mode
      7. 7.5.7  I2S Mode
      8. 7.5.8  DSP Mode
      9. 7.5.9  TDM Data Transfer
      10. 7.5.10 Audio Clock Generation
  9. 8 Register Maps
    1. 8.1 Output Stage Volume Controls
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 External Speaker Driver in Infotainment and Cluster Applications
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 External Speaker Amplifier With Separate Line Outputs
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Device Nomenclature
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Community Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

7.3.19 Jack and Headset Detection

The TLV320AIC3104-Q1 includes extensive capability to monitor a headphone, microphone, or headset jack, determine if a plug has been inserted into the jack, and then determine what type of headset or headphone is wired to the plug. Figure 7-8 shows one configuration of the device that enables detection and determination of headset type when a pseudo-differential (capacitor free) mono headphone output configuration is used. The registers used for this function are registers 14, 96, 97, and 13, page 0. The type of headset detected can be read back from register 13, page 0. For best results, select a MICBIAS value as high as possible and program the output driver common-mode level at a 1.35-V or 1.5-V level.

TLV320AIC3104-Q1 Configuration of Device for Jack Detection Using Pseudo-Differential (Capless) Headphone Output Connection Figure 7-8 Configuration of Device for Jack Detection Using Pseudo-Differential (Capless) Headphone Output Connection

A modified output configuration used when the output drivers are AC-coupled is shown in Figure 7-9. Note that in this mode, the device cannot accurately determine if the inserted headphone is a mono or stereo headphone.

TLV320AIC3104-Q1 Configuration of Device for Jack Detection Using AC-Coupled Stereo Headphone Output Connection Figure 7-9 Configuration of Device for Jack Detection Using AC-Coupled Stereo Headphone Output Connection

An output configuration for the case of the outputs driving fully differential stereo headphones is shown in Figure 7-10. In this mode, there is a requirement on the jack side that either HPLCOM or HPLOUT get shorted to ground if the plug is removed, which can be implemented using a spring terminal in a jack. For this mode to function properly, short-circuit detection should be enabled and configured to power down the drivers if a short\u0002circuit is detected. The registers that control this functionality are in page 0, register 38, bits D2 to D1.

TLV320AIC3104-Q1 Configuration of Device for Jack Detection Using Fully-Differential Stereo Headphone Output Connection Figure 7-10 Configuration of Device for Jack Detection Using Fully-Differential Stereo Headphone Output Connection